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3f23d4b8c3
tryLatency compares two sched candidates. For the top zone it prefers the one with lesser depth, but only if that depth is greater than the total latency of the instructions we've already scheduled -- otherwise its latency would be hidden and there would be no stall. Unfortunately it only tests the depth of one of the candidates. This can lead to situations where the TopDepthReduce heuristic does not kick in, but a lower priority heuristic chooses the other candidate, whose depth *is* greater than the already scheduled latency, which causes a stall. The fix is to apply the heuristic if the depth of *either* candidate is greater than the already scheduled latency. All this also applies to the BotHeightReduce heuristic in the bottom zone. Differential Revision: https://reviews.llvm.org/D72392
328 lines
10 KiB
LLVM
328 lines
10 KiB
LLVM
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE
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; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE
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; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8LE
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; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE
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; Function Attrs: norecurse nounwind readonly
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define <4 x i32> @s2v_test1(i32* nocapture readonly %int32, <4 x i32> %vec) {
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; P8LE-LABEL: s2v_test1:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: addis r4, r2, .LCPI0_0@toc@ha
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; P8LE-NEXT: lxsiwzx v4, 0, r3
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; P8LE-NEXT: addi r4, r4, .LCPI0_0@toc@l
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; P8LE-NEXT: lvx v3, 0, r4
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; P8LE-NEXT: vperm v2, v2, v4, v3
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; P8LE-NEXT: blr
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; P8BE-LABEL: s2v_test1:
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; P8BE: # %bb.0: # %entry
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; P8BE: lfiwzx f0, 0, r3
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; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
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; P8BE: xxsldwi vs0, v2, vs0, 1
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; P8BE: xxsldwi v2, vs0, vs0, 3
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; P8BE-NEXT: blr
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entry:
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%0 = load i32, i32* %int32, align 4
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%vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
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ret <4 x i32> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <4 x i32> @s2v_test2(i32* nocapture readonly %int32, <4 x i32> %vec) {
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; P8LE-LABEL: s2v_test2:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
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; P8LE-NEXT: addi r3, r3, 4
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; P8LE-NEXT: addi r4, r4, .LCPI1_0@toc@l
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; P8LE-NEXT: lxsiwzx v4, 0, r3
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; P8LE-NEXT: lvx v3, 0, r4
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; P8LE-NEXT: vperm v2, v2, v4, v3
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; P8LE-NEXT: blr
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; P8BE-LABEL: s2v_test2:
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; P8BE: # %bb.0: # %entry
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; P8BE: addi r3, r3, 4
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; P8BE: lfiwzx f0, 0, r3
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; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
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; P8BE: xxsldwi vs0, v2, vs0, 1
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; P8BE: xxsldwi v2, vs0, vs0, 3
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; P8BE-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds i32, i32* %int32, i64 1
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%0 = load i32, i32* %arrayidx, align 4
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%vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
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ret <4 x i32> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <4 x i32> @s2v_test3(i32* nocapture readonly %int32, <4 x i32> %vec, i32 signext %Idx) {
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; P8LE-LABEL: s2v_test3:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
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; P8LE-NEXT: sldi r5, r7, 2
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; P8LE-NEXT: addi r4, r4, .LCPI2_0@toc@l
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; P8LE-NEXT: lxsiwzx v3, r3, r5
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; P8LE-NEXT: lvx v4, 0, r4
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; P8LE-NEXT: vperm v2, v2, v3, v4
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; P8LE-NEXT: blr
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; P8BE-LABEL: s2v_test3:
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; P8BE: # %bb.0: # %entry
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; P8BE: sldi r4, r7, 2
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; P8BE: lfiwzx f0, r3, r4
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; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
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; P8BE: xxsldwi vs0, v2, vs0, 1
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; P8BE: xxsldwi v2, vs0, vs0, 3
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; P8BE-NEXT: blr
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entry:
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%idxprom = sext i32 %Idx to i64
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%arrayidx = getelementptr inbounds i32, i32* %int32, i64 %idxprom
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%0 = load i32, i32* %arrayidx, align 4
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%vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
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ret <4 x i32> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <4 x i32> @s2v_test4(i32* nocapture readonly %int32, <4 x i32> %vec) {
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; P8LE-LABEL: s2v_test4:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
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; P8LE-NEXT: addi r3, r3, 4
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; P8LE-NEXT: addi r4, r4, .LCPI3_0@toc@l
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; P8LE-NEXT: lxsiwzx v4, 0, r3
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; P8LE-NEXT: lvx v3, 0, r4
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; P8LE-NEXT: vperm v2, v2, v4, v3
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; P8LE-NEXT: blr
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; P8BE-LABEL: s2v_test4:
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; P8BE: # %bb.0: # %entry
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; P8BE: addi r3, r3, 4
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; P8BE: lfiwzx f0, 0, r3
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; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
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; P8BE: xxsldwi vs0, v2, vs0, 1
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; P8BE: xxsldwi v2, vs0, vs0, 3
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; P8BE-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds i32, i32* %int32, i64 1
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%0 = load i32, i32* %arrayidx, align 4
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%vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
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ret <4 x i32> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <4 x i32> @s2v_test5(<4 x i32> %vec, i32* nocapture readonly %ptr1) {
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; P8LE-LABEL: s2v_test5:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
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; P8LE-NEXT: lxsiwzx v4, 0, r5
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; P8LE-NEXT: addi r3, r3, .LCPI4_0@toc@l
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; P8LE-NEXT: lvx v3, 0, r3
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; P8LE-NEXT: vperm v2, v2, v4, v3
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; P8LE-NEXT: blr
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; P8BE-LABEL: s2v_test5:
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; P8BE: # %bb.0: # %entry
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; P8BE: lfiwzx f0, 0, r5
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; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
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; P8BE: xxsldwi vs0, v2, vs0, 1
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; P8BE: xxsldwi v2, vs0, vs0, 3
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; P8BE-NEXT: blr
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entry:
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%0 = load i32, i32* %ptr1, align 4
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%vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
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ret <4 x i32> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <4 x float> @s2v_test_f1(float* nocapture readonly %f64, <4 x float> %vec) {
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; P8LE-LABEL: s2v_test_f1:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
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; P8LE-NEXT: lxsiwzx v4, 0, r3
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; P8LE-NEXT: addi r4, r4, .LCPI5_0@toc@l
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; P8LE-NEXT: lvx v3, 0, r4
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; P8LE-NEXT: vperm v2, v2, v4, v3
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; P8LE-NEXT: blr
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; P8BE-LABEL: s2v_test_f1:
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; P8BE: # %bb.0: # %entry
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; P8BE: lfiwzx f0, 0, r3
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; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
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; P8BE: xxsldwi vs0, v2, vs0, 1
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; P8BE: xxsldwi v2, vs0, vs0, 3
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; P8BE-NEXT: blr
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entry:
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%0 = load float, float* %f64, align 4
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%vecins = insertelement <4 x float> %vec, float %0, i32 0
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ret <4 x float> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <2 x float> @s2v_test_f2(float* nocapture readonly %f64, <2 x float> %vec) {
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; P9LE-LABEL: s2v_test_f2:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: addi r3, r3, 4
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; P9LE-NEXT: vmrglw v2, v2, v2
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; P9LE-NEXT: lxsiwzx v3, 0, r3
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; P9LE-NEXT: vmrghw v2, v2, v3
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; P9LE-NEXT: blr
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; P9BE-LABEL: s2v_test_f2:
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; P9BE: # %bb.0: # %entry
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; P9BE: addi r3, r3, 4
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; P9BE-DAG: xxspltw v2, v2, 1
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; P9BE-DAG: lfiwzx f0, 0, r3
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; P9BE-NEXT: xxsldwi v3, f0, f0, 1
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; P9BE: vmrghw v2, v3, v2
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; P9BE-NEXT: blr
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; P8LE-LABEL: s2v_test_f2:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: vmrglw v2, v2, v2
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; P8LE-NEXT: addi r3, r3, 4
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; P8LE-NEXT: lxsiwzx v3, 0, r3
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; P8LE-NEXT: vmrghw v2, v2, v3
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; P8LE-NEXT: blr
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; P8BE-LABEL: s2v_test_f2:
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; P8BE: # %bb.0: # %entry
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; P8BE-NEXT: addi r3, r3, 4
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; P8BE-NEXT: xxspltw v2, v2, 1
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; P8BE-NEXT: lfiwzx f0, 0, r3
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; P8BE-NEXT: xxsldwi v3, f0, f0, 1
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; P8BE-NEXT: vmrghw v2, v3, v2
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; P8BE-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds float, float* %f64, i64 1
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%0 = load float, float* %arrayidx, align 8
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%vecins = insertelement <2 x float> %vec, float %0, i32 0
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ret <2 x float> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <2 x float> @s2v_test_f3(float* nocapture readonly %f64, <2 x float> %vec, i32 signext %Idx) {
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; P9LE-LABEL: s2v_test_f3:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: sldi r4, r7, 2
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; P9LE-NEXT: vmrglw v2, v2, v2
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; P9LE-NEXT: lxsiwzx v3, r3, r4
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; P9LE-NEXT: vmrghw v2, v2, v3
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; P9LE-NEXT: blr
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; P9BE-LABEL: s2v_test_f3:
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; P9BE: # %bb.0: # %entry
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; P9BE: sldi r4, r7, 2
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; P9BE-DAG: lfiwzx f0, r3, r4
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; P9BE-DAG: xxspltw v2, v2, 1
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; P9BE: xxsldwi v3, f0, f0, 1
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; P9BE: vmrghw v2, v3, v2
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; P9BE-NEXT: blr
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; P8LE-LABEL: s2v_test_f3:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: vmrglw v2, v2, v2
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; P8LE-NEXT: sldi r4, r7, 2
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; P8LE-NEXT: lxsiwzx v3, r3, r4
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; P8LE-NEXT: vmrghw v2, v2, v3
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; P8LE-NEXT: blr
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; P8BE-LABEL: s2v_test_f3:
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; P8BE: # %bb.0: # %entry
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; P8BE-NEXT: sldi r4, r7, 2
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; P8BE-NEXT: xxspltw v2, v2, 1
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; P8BE-NEXT: lfiwzx f0, r3, r4
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; P8BE-NEXT: xxsldwi v3, f0, f0, 1
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; P8BE-NEXT: vmrghw v2, v3, v2
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; P8BE-NEXT: blr
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entry:
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%idxprom = sext i32 %Idx to i64
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%arrayidx = getelementptr inbounds float, float* %f64, i64 %idxprom
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%0 = load float, float* %arrayidx, align 8
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%vecins = insertelement <2 x float> %vec, float %0, i32 0
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ret <2 x float> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <2 x float> @s2v_test_f4(float* nocapture readonly %f64, <2 x float> %vec) {
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; P9LE-LABEL: s2v_test_f4:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: addi r3, r3, 4
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; P9LE-NEXT: vmrglw v2, v2, v2
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; P9LE-NEXT: lxsiwzx v3, 0, r3
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; P9LE-NEXT: vmrghw v2, v2, v3
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; P9LE-NEXT: blr
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; P9BE-LABEL: s2v_test_f4:
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; P9BE: # %bb.0: # %entry
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; P9BE: addi r3, r3, 4
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; P9BE-DAG: lfiwzx f0, 0, r3
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; P9BE-DAG: xxspltw v2, v2, 1
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; P9BE: xxsldwi v3, f0, f0, 1
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; P9BE: vmrghw v2, v3, v2
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; P9BE-NEXT: blr
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; P8LE-LABEL: s2v_test_f4:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: vmrglw v2, v2, v2
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; P8LE-NEXT: addi r3, r3, 4
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; P8LE-NEXT: lxsiwzx v3, 0, r3
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; P8LE-NEXT: vmrghw v2, v2, v3
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; P8LE-NEXT: blr
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; P8BE-LABEL: s2v_test_f4:
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; P8BE: # %bb.0: # %entry
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; P8BE-NEXT: addi r3, r3, 4
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; P8BE-NEXT: xxspltw v2, v2, 1
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; P8BE-NEXT: lfiwzx f0, 0, r3
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; P8BE-NEXT: xxsldwi v3, f0, f0, 1
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; P8BE-NEXT: vmrghw v2, v3, v2
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; P8BE-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds float, float* %f64, i64 1
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%0 = load float, float* %arrayidx, align 8
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%vecins = insertelement <2 x float> %vec, float %0, i32 0
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ret <2 x float> %vecins
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}
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; Function Attrs: norecurse nounwind readonly
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define <2 x float> @s2v_test_f5(<2 x float> %vec, float* nocapture readonly %ptr1) {
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; P9LE-LABEL: s2v_test_f5:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: lxsiwzx v3, 0, r5
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; P9LE-NEXT: vmrglw v2, v2, v2
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; P9LE-NEXT: vmrghw v2, v2, v3
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; P9LE-NEXT: blr
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; P9BE-LABEL: s2v_test_f5:
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; P9BE: # %bb.0: # %entry
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; P9BE: lfiwzx f0, 0, r5
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; P9BE: xxspltw v2, v2, 1
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; P9BE-NEXT: xxsldwi v3, f0, f0, 1
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; P9BE: vmrghw v2, v3, v2
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; P9BE-NEXT: blr
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; P8LE-LABEL: s2v_test_f5:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: vmrglw v2, v2, v2
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; P8LE-NEXT: lxsiwzx v3, 0, r5
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; P8LE-NEXT: vmrghw v2, v2, v3
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; P8LE-NEXT: blr
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; P8BE-LABEL: s2v_test_f5:
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; P8BE: # %bb.0: # %entry
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; P8BE-NEXT: lfiwzx f0, 0, r5
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; P8BE-NEXT: xxspltw v2, v2, 1
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; P8BE-NEXT: xxsldwi v3, f0, f0, 1
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; P8BE-NEXT: vmrghw v2, v3, v2
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; P8BE-NEXT: blr
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entry:
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%0 = load float, float* %ptr1, align 8
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%vecins = insertelement <2 x float> %vec, float %0, i32 0
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ret <2 x float> %vecins
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}
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