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cfc303a827
Using `clr reg`/`mov %g0, reg`/`or %g0, %g0, reg` to zero a register looks much better than `sethi 0, reg`. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D45810 llvm-svn: 330396
20 lines
647 B
LLVM
20 lines
647 B
LLVM
; RUN: llc -march=sparc < %s | FileCheck %s
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; If computeKnownSignBits (in SelectionDAG) can do a simple
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; look-thru for extractelement then we know that the add will yield a
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; non-negative result.
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define i1 @test1(<4 x i16>* %in) {
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; CHECK-LABEL: ! %bb.0:
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; CHECK-NEXT: retl
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; CHECK-NEXT: mov %g0, %o0
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%vec2 = load <4 x i16>, <4 x i16>* %in, align 1
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%vec3 = lshr <4 x i16> %vec2, <i16 2, i16 2, i16 2, i16 2>
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%vec4 = sext <4 x i16> %vec3 to <4 x i32>
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%elt0 = extractelement <4 x i32> %vec4, i32 0
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%elt1 = extractelement <4 x i32> %vec4, i32 1
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%sum = add i32 %elt0, %elt1
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%bool = icmp slt i32 %sum, 0
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ret i1 %bool
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}
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