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bb4ad38d95
VE has only 64 bits AND/OR/XOR instructions. We pretended that VE has 32 bits instructions also, but doing it increase the number of generated instructions. Therefore, we decide to promote 32 bits operations and use only 64 bits instructions in back end. We also avoid pretending that VE has 32 bits LEA instruction. Update regression tests also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D85726
183 lines
4.9 KiB
LLVM
183 lines
4.9 KiB
LLVM
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
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declare i128 @llvm.cttz.i128(i128, i1)
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declare i64 @llvm.cttz.i64(i64, i1)
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declare i32 @llvm.cttz.i32(i32, i1)
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declare i16 @llvm.cttz.i16(i16, i1)
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declare i8 @llvm.cttz.i8(i8, i1)
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define i128 @func128(i128 %p) {
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; CHECK-LABEL: func128:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s2, 0, (0)1
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; CHECK-NEXT: cmps.l %s3, %s0, %s2
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; CHECK-NEXT: lea %s4, -1(, %s0)
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; CHECK-NEXT: nnd %s0, %s0, %s4
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; CHECK-NEXT: pcnt %s4, %s0
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; CHECK-NEXT: lea %s0, -1(, %s1)
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; CHECK-NEXT: nnd %s0, %s1, %s0
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; CHECK-NEXT: pcnt %s0, %s0
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; CHECK-NEXT: lea %s0, 64(, %s0)
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; CHECK-NEXT: cmov.l.ne %s0, %s4, %s3
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; CHECK-NEXT: or %s1, 0, %s2
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i128 @llvm.cttz.i128(i128 %p, i1 true)
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ret i128 %r
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}
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define i64 @func64(i64 %p) {
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; CHECK-LABEL: func64:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s1, -1(, %s0)
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; CHECK-NEXT: nnd %s0, %s0, %s1
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; CHECK-NEXT: pcnt %s0, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i64 @llvm.cttz.i64(i64 %p, i1 true)
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ret i64 %r
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}
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define signext i32 @func32s(i32 signext %p) {
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; CHECK-LABEL: func32s:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s1, -1, %s0
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; CHECK-NEXT: nnd %s0, %s0, %s1
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: pcnt %s0, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true)
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ret i32 %r
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}
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define zeroext i32 @func32z(i32 zeroext %p) {
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; CHECK-LABEL: func32z:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s1, -1, %s0
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; CHECK-NEXT: nnd %s0, %s0, %s1
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: pcnt %s0, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true)
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ret i32 %r
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}
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define signext i16 @func16s(i16 signext %p) {
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; CHECK-LABEL: func16s:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s1, -1, %s0
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; CHECK-NEXT: nnd %s0, %s0, %s1
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: pcnt %s0, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true)
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ret i16 %r
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}
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define zeroext i16 @func16z(i16 zeroext %p) {
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; CHECK-LABEL: func16z:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s1, -1, %s0
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; CHECK-NEXT: nnd %s0, %s0, %s1
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: pcnt %s0, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true)
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ret i16 %r
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}
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define signext i8 @func8s(i8 signext %p) {
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; CHECK-LABEL: func8s:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s1, -1, %s0
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; CHECK-NEXT: nnd %s0, %s0, %s1
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: pcnt %s0, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true)
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ret i8 %r
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}
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define zeroext i8 @func8z(i8 zeroext %p) {
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; CHECK-LABEL: func8z:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s1, -1, %s0
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; CHECK-NEXT: nnd %s0, %s0, %s1
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: pcnt %s0, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true)
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ret i8 %r
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}
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define i128 @func128i() {
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; CHECK-LABEL: func128i:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s0, 8, (0)1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i128 @llvm.cttz.i128(i128 65280, i1 true)
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ret i128 %r
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}
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define i64 @func64i() {
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; CHECK-LABEL: func64i:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s0, 8, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i64 @llvm.cttz.i64(i64 65280, i1 true)
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ret i64 %r
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}
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define signext i32 @func32is() {
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; CHECK-LABEL: func32is:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s0, 8, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i32 @llvm.cttz.i32(i32 65280, i1 true)
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ret i32 %r
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}
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define zeroext i32 @func32iz() {
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; CHECK-LABEL: func32iz:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s0, 8, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i32 @llvm.cttz.i32(i32 65280, i1 true)
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ret i32 %r
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}
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define signext i16 @func16is() {
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; CHECK-LABEL: func16is:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s0, 8, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i16 @llvm.cttz.i16(i16 65280, i1 true)
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ret i16 %r
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}
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define zeroext i16 @func16iz() {
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; CHECK-LABEL: func16iz:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s0, 8, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i16 @llvm.cttz.i16(i16 65280, i1 true)
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ret i16 %r
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}
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define signext i8 @func8is() {
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; CHECK-LABEL: func8is:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s0, 4, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i8 @llvm.cttz.i8(i8 240, i1 true)
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ret i8 %r
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}
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define zeroext i8 @func8iz() {
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; CHECK-LABEL: func8iz:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s0, 4, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%r = tail call i8 @llvm.cttz.i8(i8 240, i1 true)
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ret i8 %r
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}
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