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847b3d4c65
Change to not generate truncate instructions if all use of a truncate operation don't care about higher bits. For example, an i32 add instruction doesn't care about higher 32 bits in 64 bit registers. Updates regression tests also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D85418
55 lines
1.5 KiB
LLVM
55 lines
1.5 KiB
LLVM
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
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define double @selectf64(i1 zeroext, double, double) {
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; CHECK-LABEL: selectf64:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: or %s0, 0, %s2
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select i1 %0, double %1, double %2
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ret double %4
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}
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define float @selectf32(i1 zeroext, float, float) {
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; CHECK-LABEL: selectf32:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: or %s0, 0, %s2
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select i1 %0, float %1, float %2
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ret float %4
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}
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define i64 @selecti64(i1 zeroext, i64, i64) {
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; CHECK-LABEL: selecti64:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: or %s0, 0, %s2
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select i1 %0, i64 %1, i64 %2
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ret i64 %4
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}
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define i32 @selecti32(i1 zeroext, i32, i32) {
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; CHECK-LABEL: selecti32:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: or %s0, 0, %s2
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select i1 %0, i32 %1, i32 %2
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ret i32 %4
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}
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define zeroext i1 @selecti1(i1 zeroext, i1 zeroext, i1 zeroext) {
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; CHECK-LABEL: selecti1:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select i1 %0, i1 %1, i1 %2
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ret i1 %4
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}
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