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https://github.com/RPCS3/llvm-mirror.git
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847b3d4c65
Change to not generate truncate instructions if all use of a truncate operation don't care about higher bits. For example, an i32 add instruction doesn't care about higher 32 bits in 64 bit registers. Updates regression tests also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D85418
132 lines
3.6 KiB
LLVM
132 lines
3.6 KiB
LLVM
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
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define zeroext i1 @setcceq(i32, i32) {
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; CHECK-LABEL: setcceq:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s1, 12, (0)1
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; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp eq i32 %0, 12
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ret i1 %3
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}
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define zeroext i1 @setccne(i32, i32) {
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; CHECK-LABEL: setccne:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s1, 12, (0)1
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; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.ne %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp ne i32 %0, 12
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ret i1 %3
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}
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define zeroext i1 @setccugt(i32, i32) {
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; CHECK-LABEL: setccugt:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s1, 12, (0)1
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; CHECK-NEXT: cmpu.w %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp ugt i32 %0, 12
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ret i1 %3
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}
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define zeroext i1 @setccuge(i32, i32) {
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; CHECK-LABEL: setccuge:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s1, 11, (0)1
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; CHECK-NEXT: cmpu.w %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp uge i32 %0, 12
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ret i1 %3
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}
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define zeroext i1 @setccult(i32, i32) {
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; CHECK-LABEL: setccult:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s1, 12, (0)1
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; CHECK-NEXT: cmpu.w %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp ult i32 %0, 12
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ret i1 %3
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}
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define zeroext i1 @setccule(i32, i32) {
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; CHECK-LABEL: setccule:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s1, 13, (0)1
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; CHECK-NEXT: cmpu.w %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp ule i32 %0, 12
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ret i1 %3
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}
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define zeroext i1 @setccsgt(i32, i32) {
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; CHECK-LABEL: setccsgt:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s1, 12, (0)1
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; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp sgt i32 %0, 12
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ret i1 %3
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}
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define zeroext i1 @setccsge(i32, i32) {
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; CHECK-LABEL: setccsge:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s1, 11, (0)1
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; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp sge i32 %0, 12
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ret i1 %3
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}
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define zeroext i1 @setccslt(i32, i32) {
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; CHECK-LABEL: setccslt:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s1, 12, (0)1
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; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp slt i32 %0, 12
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ret i1 %3
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}
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define zeroext i1 @setccsle(i32, i32) {
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; CHECK-LABEL: setccsle:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s1, 13, (0)1
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; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp sle i32 %0, 12
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ret i1 %3
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}
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