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https://github.com/RPCS3/llvm-mirror.git
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d49cb60862
Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
94 lines
2.8 KiB
YAML
94 lines
2.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
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--- |
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define float @test_fmul_float(float %arg1, float %arg2) {
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%ret = fmul float %arg1, %arg2
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ret float %ret
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}
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define double @test_fmul_double(double %arg1, double %arg2) {
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%ret = fmul double %arg1, %arg2
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ret double %ret
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}
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...
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---
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name: test_fmul_float
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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- { id: 2, class: _, preferred-register: '' }
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- { id: 3, class: _, preferred-register: '' }
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- { id: 4, class: _, preferred-register: '' }
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- { id: 5, class: _, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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body: |
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bb.1 (%ir-block.0):
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liveins: $xmm0, $xmm1
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; CHECK-LABEL: name: test_fmul_float
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; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
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; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
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; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
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; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[TRUNC]], [[TRUNC1]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FMUL]](s32)
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; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
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; CHECK: RET 0, implicit $xmm0
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%2:_(s128) = COPY $xmm0
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%0:_(s32) = G_TRUNC %2(s128)
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%3:_(s128) = COPY $xmm1
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%1:_(s32) = G_TRUNC %3(s128)
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%4:_(s32) = G_FMUL %0, %1
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%5:_(s128) = G_ANYEXT %4(s32)
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$xmm0 = COPY %5(s128)
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RET 0, implicit $xmm0
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...
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---
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name: test_fmul_double
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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- { id: 2, class: _, preferred-register: '' }
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- { id: 3, class: _, preferred-register: '' }
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- { id: 4, class: _, preferred-register: '' }
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- { id: 5, class: _, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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body: |
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bb.1 (%ir-block.0):
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liveins: $xmm0, $xmm1
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; CHECK-LABEL: name: test_fmul_double
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; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
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; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
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; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
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; CHECK: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[TRUNC]], [[TRUNC1]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FMUL]](s64)
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; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
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; CHECK: RET 0, implicit $xmm0
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%2:_(s128) = COPY $xmm0
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%0:_(s64) = G_TRUNC %2(s128)
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%3:_(s128) = COPY $xmm1
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%1:_(s64) = G_TRUNC %3(s128)
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%4:_(s64) = G_FMUL %0, %1
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%5:_(s128) = G_ANYEXT %4(s64)
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$xmm0 = COPY %5(s128)
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RET 0, implicit $xmm0
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...
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