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https://github.com/RPCS3/llvm-mirror.git
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d49cb60862
Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
125 lines
3.0 KiB
YAML
125 lines
3.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
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--- |
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define void @test_sub_v16i8() {
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%ret = sub <16 x i8> undef, undef
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ret void
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}
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define void @test_sub_v8i16() {
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%ret = sub <8 x i16> undef, undef
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ret void
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}
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define void @test_sub_v4i32() {
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%ret = sub <4 x i32> undef, undef
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ret void
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}
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define void @test_sub_v2i64() {
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%ret = sub <2 x i64> undef, undef
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ret void
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}
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...
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---
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name: test_sub_v16i8
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $xmm0, $xmm1
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; ALL-LABEL: name: test_sub_v16i8
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; ALL: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
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; ALL: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
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; ALL: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[DEF]], [[DEF1]]
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; ALL: RET 0
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%0(<16 x s8>) = IMPLICIT_DEF
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%1(<16 x s8>) = IMPLICIT_DEF
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%2(<16 x s8>) = G_SUB %0, %1
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$xmm0 = COPY %2
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RET 0
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...
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---
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name: test_sub_v8i16
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $xmm0, $xmm1
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; ALL-LABEL: name: test_sub_v8i16
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; ALL: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
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; ALL: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
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; ALL: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[DEF]], [[DEF1]]
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; ALL: RET 0
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%0(<8 x s16>) = IMPLICIT_DEF
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%1(<8 x s16>) = IMPLICIT_DEF
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%2(<8 x s16>) = G_SUB %0, %1
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$xmm0 = COPY %2
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RET 0
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...
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---
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name: test_sub_v4i32
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $xmm0, $xmm1
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; ALL-LABEL: name: test_sub_v4i32
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; ALL: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
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; ALL: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
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; ALL: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[DEF]], [[DEF1]]
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; ALL: RET 0
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%0(<4 x s32>) = IMPLICIT_DEF
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%1(<4 x s32>) = IMPLICIT_DEF
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%2(<4 x s32>) = G_SUB %0, %1
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$xmm0 = COPY %2
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RET 0
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...
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---
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name: test_sub_v2i64
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $xmm0, $xmm1
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; ALL-LABEL: name: test_sub_v2i64
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; ALL: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
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; ALL: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
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; ALL: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[DEF]], [[DEF1]]
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; ALL: RET 0
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%0(<2 x s64>) = IMPLICIT_DEF
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%1(<2 x s64>) = IMPLICIT_DEF
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%2(<2 x s64>) = G_SUB %0, %1
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$xmm0 = COPY %2
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RET 0
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...
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