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1d52f2e8fe
If we lower a v2i64 shuffle to PSHUFD, we currently clamp undef elements to 0, (elements 0,1 of the v4i32) which can result in the shuffle referencing more elements of the source vector than expected, affecting later shuffle combines and KnownBits/SimplifyDemanded calls. By ensuring we widen the undef mask element we allow getV4X86ShuffleImm8 to use inline elements as the default, which are more likely to fold.
89 lines
2.8 KiB
LLVM
89 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X64
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define i128 @add_i128(i128 %x, i128 %y) nounwind {
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; X86-LABEL: add_i128:
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; X86: # %bb.0:
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X86-NEXT: addl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: adcl {{[0-9]+}}(%esp), %edi
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; X86-NEXT: adcl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: adcl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: addl $1, %esi
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; X86-NEXT: adcl $0, %edi
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; X86-NEXT: adcl $0, %edx
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; X86-NEXT: adcl $0, %ecx
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; X86-NEXT: movl %esi, (%eax)
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; X86-NEXT: movl %edi, 4(%eax)
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; X86-NEXT: movl %edx, 8(%eax)
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; X86-NEXT: movl %ecx, 12(%eax)
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: retl $4
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;
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; X64-LABEL: add_i128:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: addq %rdx, %rax
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; X64-NEXT: adcq %rcx, %rsi
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; X64-NEXT: addq $1, %rax
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; X64-NEXT: adcq $0, %rsi
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; X64-NEXT: movq %rsi, %rdx
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; X64-NEXT: retq
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%t0 = add i128 %x, 1
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%t1 = add i128 %y, %t0
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ret i128 %t1
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}
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; PR42486
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define <1 x i128> @add_v1i128(<1 x i128> %x, <1 x i128> %y) nounwind {
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; X86-LABEL: add_v1i128:
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; X86: # %bb.0:
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X86-NEXT: addl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: adcl {{[0-9]+}}(%esp), %edi
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; X86-NEXT: adcl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: adcl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: addl $1, %esi
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; X86-NEXT: adcl $0, %edi
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; X86-NEXT: adcl $0, %edx
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; X86-NEXT: adcl $0, %ecx
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; X86-NEXT: movl %esi, (%eax)
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; X86-NEXT: movl %edi, 4(%eax)
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; X86-NEXT: movl %edx, 8(%eax)
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; X86-NEXT: movl %ecx, 12(%eax)
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: retl $4
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;
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; X64-LABEL: add_v1i128:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: addq %rdx, %rax
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; X64-NEXT: adcq %rcx, %rsi
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; X64-NEXT: movq %rax, %xmm0
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; X64-NEXT: movq %rsi, %xmm1
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; X64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
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; X64-NEXT: movq %xmm0, %rdx
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; X64-NEXT: addq $1, %rax
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; X64-NEXT: adcq $0, %rdx
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; X64-NEXT: retq
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%t0 = add <1 x i128> %x, <i128 1>
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%t1 = add <1 x i128> %y, %t0
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ret <1 x i128> %t1
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}
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