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f95c166dc6
We already promote SRL and SHL to i32. This will introduce sign extends sometimes which might be harder to deal with than the zero we use for promoting SRL. I ran this through some of our internal benchmark lists and didn't see any major regressions. I think there might be some DAG combine improvement opportunities in the test changes here. Differential Revision: https://reviews.llvm.org/D60278 llvm-svn: 357743
123 lines
3.5 KiB
LLVM
123 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86 --check-prefix=X86-NO-CMOV
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+cmov | FileCheck %s --check-prefix=X86 --check-prefix=X86-CMOV
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
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;; Integer absolute value, should produce something at least as good as:
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;; movl %edi, %eax
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;; negl %eax
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;; cmovll %edi, %eax
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;; ret
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; rdar://10695237
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define i8 @test_i8(i8 %a) nounwind {
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; X86-LABEL: test_i8:
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; X86: # %bb.0:
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; X86-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-NEXT: movl %eax, %ecx
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; X86-NEXT: sarb $7, %cl
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; X86-NEXT: addb %cl, %al
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; X86-NEXT: xorb %cl, %al
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; X86-NEXT: retl
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;
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; X64-LABEL: test_i8:
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; X64: # %bb.0:
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; X64-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-NEXT: movl %edi, %ecx
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; X64-NEXT: sarb $7, %cl
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; X64-NEXT: leal (%rdi,%rcx), %eax
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; X64-NEXT: xorb %cl, %al
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: retq
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%tmp1neg = sub i8 0, %a
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%b = icmp sgt i8 %a, -1
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%abs = select i1 %b, i8 %a, i8 %tmp1neg
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ret i8 %abs
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}
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define i16 @test_i16(i16 %a) nounwind {
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; X86-NO-CMOV-LABEL: test_i16:
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; X86-NO-CMOV: # %bb.0:
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; X86-NO-CMOV-NEXT: movswl {{[0-9]+}}(%esp), %eax
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; X86-NO-CMOV-NEXT: movl %eax, %ecx
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; X86-NO-CMOV-NEXT: sarl $15, %ecx
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; X86-NO-CMOV-NEXT: addl %ecx, %eax
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; X86-NO-CMOV-NEXT: xorl %ecx, %eax
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; X86-NO-CMOV-NEXT: # kill: def $ax killed $ax killed $eax
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; X86-NO-CMOV-NEXT: retl
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;
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; X86-CMOV-LABEL: test_i16:
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; X86-CMOV: # %bb.0:
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; X86-CMOV-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
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; X86-CMOV-NEXT: movl %ecx, %eax
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; X86-CMOV-NEXT: negw %ax
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; X86-CMOV-NEXT: cmovlw %cx, %ax
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; X86-CMOV-NEXT: retl
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;
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; X64-LABEL: test_i16:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: negw %ax
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; X64-NEXT: cmovlw %di, %ax
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; X64-NEXT: retq
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%tmp1neg = sub i16 0, %a
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%b = icmp sgt i16 %a, -1
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%abs = select i1 %b, i16 %a, i16 %tmp1neg
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ret i16 %abs
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}
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define i32 @test_i32(i32 %a) nounwind {
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; X86-NO-CMOV-LABEL: test_i32:
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; X86-NO-CMOV: # %bb.0:
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; X86-NO-CMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NO-CMOV-NEXT: movl %eax, %ecx
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; X86-NO-CMOV-NEXT: sarl $31, %ecx
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; X86-NO-CMOV-NEXT: addl %ecx, %eax
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; X86-NO-CMOV-NEXT: xorl %ecx, %eax
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; X86-NO-CMOV-NEXT: retl
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;
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; X86-CMOV-LABEL: test_i32:
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; X86-CMOV: # %bb.0:
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; X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-CMOV-NEXT: movl %ecx, %eax
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; X86-CMOV-NEXT: negl %eax
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; X86-CMOV-NEXT: cmovll %ecx, %eax
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; X86-CMOV-NEXT: retl
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;
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; X64-LABEL: test_i32:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: negl %eax
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; X64-NEXT: cmovll %edi, %eax
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; X64-NEXT: retq
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%tmp1neg = sub i32 0, %a
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%b = icmp sgt i32 %a, -1
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%abs = select i1 %b, i32 %a, i32 %tmp1neg
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ret i32 %abs
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}
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define i64 @test_i64(i64 %a) nounwind {
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; X86-LABEL: test_i64:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl %edx, %ecx
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; X86-NEXT: sarl $31, %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: addl %ecx, %eax
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; X86-NEXT: adcl %ecx, %edx
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; X86-NEXT: xorl %ecx, %edx
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; X86-NEXT: xorl %ecx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_i64:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: negq %rax
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; X64-NEXT: cmovlq %rdi, %rax
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; X64-NEXT: retq
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%tmp1neg = sub i64 0, %a
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%b = icmp sgt i64 %a, -1
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%abs = select i1 %b, i64 %a, i64 %tmp1neg
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ret i64 %abs
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}
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