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329a30125b
The SchedModel allows the addition of ReadAdvances to express that certain operands of the instructions are needed at a later point than the others. RegAlloc may add pseudo operands that are not part of the instruction descriptor, and therefore cannot have any read advance entries. This meant that in some cases the desired read advance was nullified by such a pseudo operand, which still had the original latency. This patch fixes this by making sure that such pseudo operands get a zero latency during DAG construction. Review: Matthias Braun, Ulrich Weigand. https://reviews.llvm.org/D49671 llvm-svn: 345606
100 lines
3.2 KiB
LLVM
100 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mcpu=pentium2 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mcpu=pentium3 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=XMM
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; RUN: llc < %s -mcpu=bdver1 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=YMM
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%struct.x = type { i16, i16 }
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define void @t() nounwind {
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; X86-LABEL: t:
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; X86: ## %bb.0: ## %entry
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; X86-NEXT: subl $44, %esp
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; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
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; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
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; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
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; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
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; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
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; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
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; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
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; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
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; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl %eax, (%esp)
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; X86-NEXT: calll _foo
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; X86-NEXT: addl $44, %esp
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; X86-NEXT: retl
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;
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; XMM-LABEL: t:
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; XMM: ## %bb.0: ## %entry
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; XMM-NEXT: subl $60, %esp
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; XMM-NEXT: xorps %xmm0, %xmm0
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; XMM-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
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; XMM-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
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; XMM-NEXT: leal {{[0-9]+}}(%esp), %eax
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; XMM-NEXT: movl %eax, (%esp)
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; XMM-NEXT: calll _foo
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; XMM-NEXT: addl $60, %esp
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; XMM-NEXT: retl
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;
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; YMM-LABEL: t:
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; YMM: ## %bb.0: ## %entry
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; YMM-NEXT: pushl %ebp
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; YMM-NEXT: movl %esp, %ebp
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; YMM-NEXT: andl $-32, %esp
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; YMM-NEXT: subl $96, %esp
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; YMM-NEXT: leal {{[0-9]+}}(%esp), %eax
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; YMM-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; YMM-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
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; YMM-NEXT: movl %eax, (%esp)
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; YMM-NEXT: vzeroupper
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; YMM-NEXT: calll _foo
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; YMM-NEXT: movl %ebp, %esp
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; YMM-NEXT: popl %ebp
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; YMM-NEXT: retl
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entry:
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%up_mvd = alloca [8 x %struct.x] ; <[8 x %struct.x]*> [#uses=2]
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%up_mvd116 = getelementptr [8 x %struct.x], [8 x %struct.x]* %up_mvd, i32 0, i32 0 ; <%struct.x*> [#uses=1]
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%tmp110117 = bitcast [8 x %struct.x]* %up_mvd to i8* ; <i8*> [#uses=1]
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call void @llvm.memset.p0i8.i64(i8* align 8 %tmp110117, i8 0, i64 32, i1 false)
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call void @foo( %struct.x* %up_mvd116 ) nounwind
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ret void
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}
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declare void @foo(%struct.x*)
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind
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; Ensure that alignment of '0' in an @llvm.memset intrinsic results in
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; unaligned loads and stores.
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define void @PR15348(i8* %a) {
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; X86-LABEL: PR15348:
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; X86: ## %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movb $0, 16(%eax)
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; X86-NEXT: movl $0, 12(%eax)
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; X86-NEXT: movl $0, 8(%eax)
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; X86-NEXT: movl $0, 4(%eax)
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; X86-NEXT: movl $0, (%eax)
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; X86-NEXT: retl
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;
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; XMM-LABEL: PR15348:
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; XMM: ## %bb.0:
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; XMM-NEXT: movl {{[0-9]+}}(%esp), %eax
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; XMM-NEXT: movb $0, 16(%eax)
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; XMM-NEXT: movl $0, 12(%eax)
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; XMM-NEXT: movl $0, 8(%eax)
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; XMM-NEXT: movl $0, 4(%eax)
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; XMM-NEXT: movl $0, (%eax)
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; XMM-NEXT: retl
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;
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; YMM-LABEL: PR15348:
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; YMM: ## %bb.0:
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; YMM-NEXT: movl {{[0-9]+}}(%esp), %eax
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; YMM-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; YMM-NEXT: vmovups %xmm0, (%eax)
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; YMM-NEXT: movb $0, 16(%eax)
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; YMM-NEXT: retl
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call void @llvm.memset.p0i8.i64(i8* %a, i8 0, i64 17, i1 false)
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ret void
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}
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