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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
22 lines
680 B
LLVM
22 lines
680 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -mattr=rdpid | FileCheck %s --check-prefix=CHECK --check-prefix=X86-64
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; RUN: llc < %s -mtriple=i686-- -mattr=rdpid | FileCheck %s --check-prefix=CHECK --check-prefix=X86
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define i32 @test_builtin_rdpid() {
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; X86-64-LABEL: test_builtin_rdpid:
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; X86-64: # %bb.0:
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; X86-64-NEXT: rdpid %rax
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; X86-64-NEXT: # kill: def $eax killed $eax killed $rax
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; X86-64-NEXT: retq
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;
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; X86-LABEL: test_builtin_rdpid:
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; X86: # %bb.0:
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; X86-NEXT: rdpid %eax
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; X86-NEXT: retl
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%1 = tail call i32 @llvm.x86.rdpid()
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ret i32 %1
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}
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declare i32 @llvm.x86.rdpid()
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