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0663a19f9d
The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
121 lines
4.9 KiB
LLVM
121 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64
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; widening shuffle v3float and then a add
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define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
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; X86-LABEL: shuf:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: addps %xmm1, %xmm0
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; X86-NEXT: extractps $2, %xmm0, 8(%eax)
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; X86-NEXT: extractps $1, %xmm0, 4(%eax)
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; X86-NEXT: movss %xmm0, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: shuf:
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; X64: # %bb.0: # %entry
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; X64-NEXT: addps %xmm1, %xmm0
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; X64-NEXT: extractps $2, %xmm0, 8(%rdi)
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; X64-NEXT: movlps %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2>
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%val = fadd <3 x float> %x, %src2
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store <3 x float> %val, <3 x float>* %dst.addr
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ret void
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}
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; widening shuffle v3float with a different mask and then a add
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define void @shuf2(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
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; X86-LABEL: shuf2:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
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; X86-NEXT: addps %xmm1, %xmm0
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; X86-NEXT: extractps $2, %xmm0, 8(%eax)
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; X86-NEXT: extractps $1, %xmm0, 4(%eax)
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; X86-NEXT: movss %xmm0, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: shuf2:
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; X64: # %bb.0: # %entry
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; X64-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
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; X64-NEXT: addps %xmm1, %xmm0
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; X64-NEXT: extractps $2, %xmm0, 8(%rdi)
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; X64-NEXT: movlps %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 4, i32 2>
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%val = fadd <3 x float> %x, %src2
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store <3 x float> %val, <3 x float>* %dst.addr
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ret void
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}
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; Example of when widening a v3float operation causes the DAG to replace a node
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; with the operation that we are currently widening, i.e. when replacing
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; opA with opB, the DAG will produce new operations with opA.
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define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) nounwind {
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; X86-LABEL: shuf3:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; X86-NEXT: movaps %xmm1, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: shuf3:
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; X64: # %bb.0: # %entry
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; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; X64-NEXT: movaps %xmm1, (%rdi)
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; X64-NEXT: retq
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entry:
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%shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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%tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
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%tmp1.i.i = shufflevector <3 x float> %tmp25.i.i, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp3.i13 = shufflevector <4 x float> %tmp1.i.i, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> ; <<3 x float>>
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%tmp6.i14 = shufflevector <3 x float> %tmp3.i13, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp97.i = shufflevector <4 x float> %tmp6.i14, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
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%tmp2.i18 = shufflevector <3 x float> %tmp97.i, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
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%t5 = bitcast <4 x float> %tmp2.i18 to <4 x i32>
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%shr.i.i19 = lshr <4 x i32> %t5, <i32 19, i32 19, i32 19, i32 19>
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%and.i.i20 = and <4 x i32> %shr.i.i19, <i32 4080, i32 4080, i32 4080, i32 4080>
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%shuffle.i.i.i21 = shufflevector <4 x float> %tmp2.i18, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
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store <4 x float> %shuffle.i.i.i21, <4 x float>* %dst
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ret void
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}
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; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS
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define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone {
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; X86-LABEL: shuf4:
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; X86: # %bb.0:
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; X86-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; X86-NEXT: retl
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;
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; X64-LABEL: shuf4:
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; X64: # %bb.0:
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; X64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; X64-NEXT: retq
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%vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i8> %vshuf
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}
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; PR11389: another CONCAT_VECTORS case
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define void @shuf5(<8 x i8>* %p) nounwind {
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; X86-LABEL: shuf5:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X86-NEXT: movsd %xmm0, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: shuf5:
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; X64: # %bb.0:
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; X64-NEXT: movabsq $2387225703656530209, %rax # imm = 0x2121212121212121
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; X64-NEXT: movq %rax, (%rdi)
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; X64-NEXT: retq
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%v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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store <8 x i8> %v, <8 x i8>* %p, align 8
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ret void
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}
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