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With SSE2, we can generate a 'movq' or other 64-bit store op on a 32-bit system even though 64-bit integers are not legal types. So instead of producing this: pshufd $229, %xmm0, %xmm1 ## xmm1 = xmm0[1,1,2,3] movd %xmm0, (%eax) movd %xmm1, 4(%eax) We can do: movq %xmm0, (%eax) This is a fix for the problem noted in D7296. Differential Revision: http://reviews.llvm.org/D9134 llvm-svn: 235460
66 lines
2.1 KiB
LLVM
66 lines
2.1 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefix=X32AVX
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; Use movq or movsd to load / store i64 values if sse2 is available.
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; rdar://6659858
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define void @foo(i64* %x, i64* %y) {
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; X64-LABEL: foo:
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; X64: # BB#0:
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; X64-NEXT: movq (%rsi), %rax
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; X64-NEXT: movq %rax, (%rdi)
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; X64-NEXT: retq
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;
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; X32-LABEL: foo:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X32-NEXT: movsd %xmm0, (%eax)
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; X32-NEXT: retl
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%tmp1 = load i64, i64* %y, align 8
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store i64 %tmp1, i64* %x, align 8
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ret void
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}
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; Verify that a 64-bit chunk extracted from a vector is stored with a movq
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; regardless of whether the system is 64-bit.
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define void @store_i64_from_vector(<8 x i16> %x, <8 x i16> %y, i64* %i) {
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; X64-LABEL: store_i64_from_vector:
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; X64: # BB#0:
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; X64-NEXT: paddw %xmm1, %xmm0
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; X64-NEXT: movq %xmm0, (%rdi)
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; X64-NEXT: retq
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;
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; X32-LABEL: store_i64_from_vector:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: paddw %xmm1, %xmm0
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; X32-NEXT: movq %xmm0, (%eax)
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; X32-NEXT: retl
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%z = add <8 x i16> %x, %y ; force execution domain
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%bc = bitcast <8 x i16> %z to <2 x i64>
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%vecext = extractelement <2 x i64> %bc, i32 0
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store i64 %vecext, i64* %i, align 8
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ret void
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}
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define void @store_i64_from_vector256(<16 x i16> %x, <16 x i16> %y, i64* %i) {
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; X32AVX-LABEL: store_i64_from_vector256:
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; X32AVX: # BB#0:
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; X32AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm0
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; X32AVX-NEXT: vextracti128 $1, %ymm0, %xmm0
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; X32AVX-NEXT: vmovq %xmm0, (%eax)
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; X32AVX-NEXT: vzeroupper
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; X32AVX-NEXT: retl
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%z = add <16 x i16> %x, %y ; force execution domain
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%bc = bitcast <16 x i16> %z to <4 x i64>
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%vecext = extractelement <4 x i64> %bc, i32 2
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store i64 %vecext, i64* %i, align 8
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ret void
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}
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