mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 11:02:59 +02:00
96c1e7e4f0
Lay out trellis-shaped CFGs optimally.
A trellis of the shape below:
A B
|\ /|
| \ / |
| X |
| / \ |
|/ \|
C D
would be laid out A; B->C ; D by the current layout algorithm. Now we identify
trellises and lay them out either A->C; B->D or A->D; B->C. This scales with an
increasing number of predecessors. A trellis is a a group of 2 or more
predecessor blocks that all have the same successors.
because of this we can tail duplicate to extend existing trellises.
As an example consider the following CFG:
B D F H
/ \ / \ / \ / \
A---C---E---G---Ret
Where A,C,E,G are all small (Currently 2 instructions).
The CFG preserving layout is then A,B,C,D,E,F,G,H,Ret.
The current code will copy C into B, E into D and G into F and yield the layout
A,C,B(C),E,D(E),F(G),G,H,ret
define void @straight_test(i32 %tag) {
entry:
br label %test1
test1: ; A
%tagbit1 = and i32 %tag, 1
%tagbit1eq0 = icmp eq i32 %tagbit1, 0
br i1 %tagbit1eq0, label %test2, label %optional1
optional1: ; B
call void @a()
br label %test2
test2: ; C
%tagbit2 = and i32 %tag, 2
%tagbit2eq0 = icmp eq i32 %tagbit2, 0
br i1 %tagbit2eq0, label %test3, label %optional2
optional2: ; D
call void @b()
br label %test3
test3: ; E
%tagbit3 = and i32 %tag, 4
%tagbit3eq0 = icmp eq i32 %tagbit3, 0
br i1 %tagbit3eq0, label %test4, label %optional3
optional3: ; F
call void @c()
br label %test4
test4: ; G
%tagbit4 = and i32 %tag, 8
%tagbit4eq0 = icmp eq i32 %tagbit4, 0
br i1 %tagbit4eq0, label %exit, label %optional4
optional4: ; H
call void @d()
br label %exit
exit:
ret void
}
here is the layout after D27742:
straight_test: # @straight_test
; ... Prologue elided
; BB#0: # %entry ; A (merged with test1)
; ... More prologue elided
mr 30, 3
andi. 3, 30, 1
bc 12, 1, .LBB0_2
; BB#1: # %test2 ; C
rlwinm. 3, 30, 0, 30, 30
beq 0, .LBB0_3
b .LBB0_4
.LBB0_2: # %optional1 ; B (copy of C)
bl a
nop
rlwinm. 3, 30, 0, 30, 30
bne 0, .LBB0_4
.LBB0_3: # %test3 ; E
rlwinm. 3, 30, 0, 29, 29
beq 0, .LBB0_5
b .LBB0_6
.LBB0_4: # %optional2 ; D (copy of E)
bl b
nop
rlwinm. 3, 30, 0, 29, 29
bne 0, .LBB0_6
.LBB0_5: # %test4 ; G
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
b .LBB0_7
.LBB0_6: # %optional3 ; F (copy of G)
bl c
nop
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
.LBB0_7: # %optional4 ; H
bl d
nop
.LBB0_8: # %exit ; Ret
ld 30, 96(1) # 8-byte Folded Reload
addi 1, 1, 112
ld 0, 16(1)
mtlr 0
blr
The tail-duplication has produced some benefit, but it has also produced a
trellis which is not laid out optimally. With this patch, we improve the layouts
of such trellises, and decrease the cost calculation for tail-duplication
accordingly.
This patch produces the layout A,C,E,G,B,D,F,H,Ret. This layout does have
back edges, which is a negative, but it has a bigger compensating
positive, which is that it handles the case where there are long strings
of skipped blocks much better than the original layout. Both layouts
handle runs of executed blocks equally well. Branch prediction also
improves if there is any correlation between subsequent optional blocks.
Here is the resulting concrete layout:
straight_test: # @straight_test
; BB#0: # %entry ; A (merged with test1)
mr 30, 3
andi. 3, 30, 1
bc 12, 1, .LBB0_4
; BB#1: # %test2 ; C
rlwinm. 3, 30, 0, 30, 30
bne 0, .LBB0_5
.LBB0_2: # %test3 ; E
rlwinm. 3, 30, 0, 29, 29
bne 0, .LBB0_6
.LBB0_3: # %test4 ; G
rlwinm. 3, 30, 0, 28, 28
bne 0, .LBB0_7
b .LBB0_8
.LBB0_4: # %optional1 ; B (Copy of C)
bl a
nop
rlwinm. 3, 30, 0, 30, 30
beq 0, .LBB0_2
.LBB0_5: # %optional2 ; D (Copy of E)
bl b
nop
rlwinm. 3, 30, 0, 29, 29
beq 0, .LBB0_3
.LBB0_6: # %optional3 ; F (Copy of G)
bl c
nop
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
.LBB0_7: # %optional4 ; H
bl d
nop
.LBB0_8: # %exit
Differential Revision: https://reviews.llvm.org/D28522
llvm-svn: 295223
141 lines
3.7 KiB
LLVM
141 lines
3.7 KiB
LLVM
; RUN: llc -O2 -o - %s | FileCheck %s
|
|
target datalayout = "e-m:e-i64:64-n32:64"
|
|
target triple = "powerpc64le-grtev4-linux-gnu"
|
|
|
|
; Intended layout:
|
|
; The code for tail-duplication during layout will produce the layout:
|
|
; test1
|
|
; test2
|
|
; body1 (with copy of test2)
|
|
; body2
|
|
; exit
|
|
|
|
;CHECK-LABEL: tail_dup_break_cfg:
|
|
;CHECK: mr [[TAGREG:[0-9]+]], 3
|
|
;CHECK: andi. {{[0-9]+}}, [[TAGREG]], 1
|
|
;CHECK-NEXT: bc 12, 1, [[BODY1LABEL:[._0-9A-Za-z]+]]
|
|
;CHECK-NEXT: # %test2
|
|
;CHECK-NEXT: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 30, 30
|
|
;CHECK-NEXT: bne 0, [[BODY2LABEL:[._0-9A-Za-z]+]]
|
|
;CHECK: [[EXITLABEL:[._0-9A-Za-z]+]]: # %exit
|
|
;CHECK: blr
|
|
;CHECK-NEXT: [[BODY1LABEL]]
|
|
;CHECK: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 30, 30
|
|
;CHECK-NEXT: beq 0, [[EXITLABEL]]
|
|
;CHECK-NEXT: [[BODY2LABEL:[._0-9A-Za-z]+]]:
|
|
;CHECK: b [[EXITLABEL]]
|
|
define void @tail_dup_break_cfg(i32 %tag) {
|
|
entry:
|
|
br label %test1
|
|
test1:
|
|
%tagbit1 = and i32 %tag, 1
|
|
%tagbit1eq0 = icmp eq i32 %tagbit1, 0
|
|
br i1 %tagbit1eq0, label %test2, label %body1, !prof !1 ; %test2 more likely
|
|
body1:
|
|
call void @a()
|
|
call void @a()
|
|
call void @a()
|
|
call void @a()
|
|
br label %test2
|
|
test2:
|
|
%tagbit2 = and i32 %tag, 2
|
|
%tagbit2eq0 = icmp eq i32 %tagbit2, 0
|
|
br i1 %tagbit2eq0, label %exit, label %body2, !prof !1 ; %exit more likely
|
|
body2:
|
|
call void @b()
|
|
call void @b()
|
|
call void @b()
|
|
call void @b()
|
|
br label %exit
|
|
exit:
|
|
ret void
|
|
}
|
|
|
|
; The branch weights here hint that we shouldn't tail duplicate in this case.
|
|
;CHECK-LABEL: tail_dup_dont_break_cfg:
|
|
;CHECK: mr [[TAGREG:[0-9]+]], 3
|
|
;CHECK: andi. {{[0-9]+}}, [[TAGREG]], 1
|
|
;CHECK-NEXT: bc 4, 1, [[TEST2LABEL:[._0-9A-Za-z]+]]
|
|
;CHECK-NEXT: # %body1
|
|
;CHECK: [[TEST2LABEL]]: # %test2
|
|
;CHECK-NEXT: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 30, 30
|
|
;CHECK-NEXT: beq 0, [[EXITLABEL:[._0-9A-Za-z]+]]
|
|
;CHECK-NEXT: # %body2
|
|
;CHECK: [[EXITLABEL:[._0-9A-Za-z]+]]: # %exit
|
|
;CHECK: blr
|
|
define void @tail_dup_dont_break_cfg(i32 %tag) {
|
|
entry:
|
|
br label %test1
|
|
test1:
|
|
%tagbit1 = and i32 %tag, 1
|
|
%tagbit1eq0 = icmp eq i32 %tagbit1, 0
|
|
br i1 %tagbit1eq0, label %test2, label %body1, !prof !1 ; %test2 more likely
|
|
body1:
|
|
call void @a()
|
|
call void @a()
|
|
call void @a()
|
|
call void @a()
|
|
br label %test2
|
|
test2:
|
|
%tagbit2 = and i32 %tag, 2
|
|
%tagbit2eq0 = icmp ne i32 %tagbit2, 0
|
|
br i1 %tagbit2eq0, label %body2, label %exit, !prof !3 ; %body2 more likely
|
|
body2:
|
|
call void @b()
|
|
call void @b()
|
|
call void @b()
|
|
call void @b()
|
|
br label %exit
|
|
exit:
|
|
ret void
|
|
}
|
|
declare void @a()
|
|
declare void @b()
|
|
declare void @c()
|
|
declare void @d()
|
|
|
|
; This function arranges for the successors of %succ to have already been laid
|
|
; out. When we consider whether to lay out succ after bb and to tail-duplicate
|
|
; it, v and ret have already been placed, so we tail-duplicate as it removes a
|
|
; branch and strictly increases fallthrough
|
|
; CHECK-LABEL: tail_dup_no_succ
|
|
; CHECK: # %entry
|
|
; CHECK: # %v
|
|
; CHECK: # %ret
|
|
; CHECK: # %bb
|
|
; CHECK: # %succ
|
|
; CHECK: # %c
|
|
; CHECK: bl c
|
|
; CHECK: rlwinm. {{[0-9]+}}, {{[0-9]+}}, 0, 29, 29
|
|
; CHECK: beq
|
|
; CHECK: b
|
|
define void @tail_dup_no_succ(i32 %tag) {
|
|
entry:
|
|
%tagbit1 = and i32 %tag, 1
|
|
%tagbit1eq0 = icmp eq i32 %tagbit1, 0
|
|
br i1 %tagbit1eq0, label %v, label %bb, !prof !2 ; %v very much more likely
|
|
bb:
|
|
%tagbit2 = and i32 %tag, 2
|
|
%tagbit2eq0 = icmp eq i32 %tagbit2, 0
|
|
br i1 %tagbit2eq0, label %succ, label %c, !prof !3 ; %succ more likely
|
|
c:
|
|
call void @c()
|
|
call void @c()
|
|
br label %succ
|
|
succ:
|
|
%tagbit3 = and i32 %tag, 4
|
|
%tagbit3eq0 = icmp eq i32 %tagbit3, 0
|
|
br i1 %tagbit3eq0, label %ret, label %v, !prof !1 ; %u more likely
|
|
v:
|
|
call void @d()
|
|
call void @d()
|
|
br label %ret
|
|
ret:
|
|
ret void
|
|
}
|
|
|
|
|
|
!1 = !{!"branch_weights", i32 5, i32 3}
|
|
!2 = !{!"branch_weights", i32 95, i32 5}
|
|
!3 = !{!"branch_weights", i32 8, i32 3}
|