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f46ad918db
This patch adds functionality in MIPS delay slot filler such as if delay slot filler have to put NOP instruction into the delay slot of microMIPS JR instruction, then instead of emitting NOP this instruction is replaced by compact jump instruction JRC. Differential Revision: http://reviews.llvm.org/D7522 llvm-svn: 229128
163 lines
5.7 KiB
LLVM
163 lines
5.7 KiB
LLVM
; RUN: llc -march=mipsel < %s | FileCheck %s
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; RUN: llc -march=mipsel -force-mips-long-branch -O3 < %s \
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; RUN: | FileCheck %s -check-prefix=O32
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; RUN: llc -march=mips64el -mcpu=mips4 -mattr=n64 -force-mips-long-branch -O3 \
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; RUN: < %s | FileCheck %s -check-prefix=N64
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; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 -force-mips-long-branch -O3 \
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; RUN: < %s | FileCheck %s -check-prefix=N64
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=micromips \
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; RUN: -force-mips-long-branch -O3 < %s | FileCheck %s -check-prefix=MICROMIPS
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; RUN: llc -mtriple=mipsel-none-nacl -force-mips-long-branch -O3 < %s \
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; RUN: | FileCheck %s -check-prefix=NACL
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@x = external global i32
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define void @test1(i32 signext %s) {
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entry:
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%cmp = icmp eq i32 %s, 0
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br i1 %cmp, label %end, label %then
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then:
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store i32 1, i32* @x, align 4
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br label %end
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end:
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ret void
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; First check the normal version (without long branch). beqz jumps to return,
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; and fallthrough block stores 1 to global variable.
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; CHECK: lui $[[R0:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[R0]], $[[R0]], %lo(_gp_disp)
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; CHECK: beqz $4, $[[BB0:BB[0-9_]+]]
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; CHECK: addu $[[GP:[0-9]+]], $[[R0]], $25
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; CHECK: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
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; CHECK: addiu $[[R2:[0-9]+]], $zero, 1
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; CHECK: sw $[[R2]], 0($[[R1]])
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; CHECK: $[[BB0]]:
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; CHECK: jr $ra
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; CHECK: nop
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; Check the MIPS32 version. Check that branch logic is inverted, so that the
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; target of the new branch (bnez) is the fallthrough block of the original
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; branch. Check that fallthrough block of the new branch contains long branch
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; expansion which at the end indirectly jumps to the target of the original
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; branch.
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; O32: lui $[[R0:[0-9]+]], %hi(_gp_disp)
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; O32: addiu $[[R0]], $[[R0]], %lo(_gp_disp)
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; O32: bnez $4, $[[BB0:BB[0-9_]+]]
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; O32: addu $[[GP:[0-9]+]], $[[R0]], $25
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; Check for long branch expansion:
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; O32: addiu $sp, $sp, -8
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; O32-NEXT: sw $ra, 0($sp)
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; O32-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
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; O32-NEXT: bal $[[BB1]]
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; O32-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]]))
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; O32-NEXT: $[[BB1]]:
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; O32-NEXT: addu $1, $ra, $1
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; O32-NEXT: lw $ra, 0($sp)
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; O32-NEXT: jr $1
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; O32-NEXT: addiu $sp, $sp, 8
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; O32: $[[BB0]]:
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; O32: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
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; O32: addiu $[[R2:[0-9]+]], $zero, 1
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; O32: sw $[[R2]], 0($[[R1]])
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; O32: $[[BB2]]:
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; O32: jr $ra
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; O32: nop
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; Check the MIPS64 version.
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; N64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test1)))
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; N64: bnez $4, $[[BB0:BB[0-9_]+]]
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; N64: daddu $[[R1:[0-9]+]], $[[R0]], $25
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; Check for long branch expansion:
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; N64: daddiu $sp, $sp, -16
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; N64-NEXT: sd $ra, 0($sp)
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; N64-NEXT: daddiu $1, $zero, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
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; N64-NEXT: dsll $1, $1, 16
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; N64-NEXT: bal $[[BB1]]
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; N64-NEXT: daddiu $1, $1, %lo(($[[BB2]])-($[[BB1]]))
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; N64-NEXT: $[[BB1]]:
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; N64-NEXT: daddu $1, $ra, $1
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; N64-NEXT: ld $ra, 0($sp)
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; N64-NEXT: jr $1
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; N64-NEXT: daddiu $sp, $sp, 16
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; N64: $[[BB0]]:
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; N64: daddiu $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1)))
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; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]])
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; N64: addiu $[[R3:[0-9]+]], $zero, 1
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; N64: sw $[[R3]], 0($[[R2]])
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; N64: $[[BB2]]:
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; N64: jr $ra
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; N64: nop
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; Check the microMIPS version.
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; MICROMIPS: lui $[[R0:[0-9]+]], %hi(_gp_disp)
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; MICROMIPS: addiu $[[R0]], $[[R0]], %lo(_gp_disp)
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; MICROMIPS: bnez $4, $[[BB0:BB[0-9_]+]]
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; MICROMIPS: addu $[[GP:[0-9]+]], $[[R0]], $25
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; Check for long branch expansion:
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; MICROMIPS: addiu $sp, $sp, -8
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; MICROMIPS-NEXT: sw $ra, 0($sp)
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; MICROMIPS-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
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; MICROMIPS-NEXT: bal $[[BB1]]
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; MICROMIPS-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]]))
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; MICROMIPS-NEXT: $[[BB1]]:
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; MICROMIPS-NEXT: addu $1, $ra, $1
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; MICROMIPS-NEXT: lw $ra, 0($sp)
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; MICROMIPS-NEXT: jr $1
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; MICROMIPS-NEXT: addiu $sp, $sp, 8
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; MICROMIPS: $[[BB0]]:
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; MICROMIPS: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
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; MICROMIPS: li16 $[[R2:[0-9]+]], 1
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; MICROMIPS: sw16 $[[R2]], 0($[[R1]])
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; MICROMIPS: $[[BB2]]:
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; MICROMIPS: jrc $ra
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; Check the NaCl version. Check that sp change is not in the branch delay slot
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; of "jr $1" instruction. Check that target of indirect branch "jr $1" is
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; bundle aligned.
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; NACL: lui $[[R0:[0-9]+]], %hi(_gp_disp)
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; NACL: addiu $[[R0]], $[[R0]], %lo(_gp_disp)
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; NACL: bnez $4, $[[BB0:BB[0-9_]+]]
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; NACL: addu $[[GP:[0-9]+]], $[[R0]], $25
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; Check for long branch expansion:
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; NACL: addiu $sp, $sp, -8
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; NACL-NEXT: sw $ra, 0($sp)
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; NACL-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
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; NACL-NEXT: bal $[[BB1]]
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; NACL-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]]))
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; NACL-NEXT: $[[BB1]]:
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; NACL-NEXT: addu $1, $ra, $1
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; NACL-NEXT: lw $ra, 0($sp)
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; NACL-NEXT: addiu $sp, $sp, 8
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; NACL-NEXT: jr $1
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; NACL-NEXT: nop
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; NACL: $[[BB0]]:
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; NACL: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
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; NACL: addiu $[[R2:[0-9]+]], $zero, 1
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; NACL: sw $[[R2]], 0($[[R1]])
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; NACL: .align 4
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; NACL-NEXT: $[[BB2]]:
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; NACL: jr $ra
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; NACL: nop
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}
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