Craig Topper 6a9e481d78 [RISCV] Cleanup comment around vector tail policy handling. NFC ... vmv.x.s and reductions don't ignore tail policy anymore.		2021-07-21 12:45:08 -07:00
..
AsmParser	[RISCV] Teach constant materialization that it can use zext.w at the end with Zba to reduce number of instructions.	2021-07-16 09:35:56 -07:00
Disassembler
MCTargetDesc	[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.	2021-07-20 09:22:06 -07:00
TargetInfo
CMakeLists.txt
RISCV.h
RISCV.td
RISCVAsmPrinter.cpp
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVExpandAtomicPseudoInsts.cpp
RISCVExpandPseudoInsts.cpp
RISCVFrameLowering.cpp	[RISCV] Avoid scalar outgoing argumetns overwriting vector frame objects.	2021-06-11 12:26:29 +08:00
RISCVFrameLowering.h
RISCVInsertVSETVLI.cpp	[RISCV] Cleanup comment around vector tail policy handling. NFC	2021-07-21 12:45:08 -07:00
RISCVInstrFormats.td
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td
RISCVInstrInfo.cpp	[RISCV] Teach constant materialization that it can use zext.w at the end with Zba to reduce number of instructions.	2021-07-16 09:35:56 -07:00
RISCVInstrInfo.h	Further improve register allocation for vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv.	2021-06-08 09:43:43 -07:00
RISCVInstrInfo.td	[RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)	2021-07-20 08:53:55 -07:00
RISCVInstrInfoA.td
RISCVInstrInfoB.td	[RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)	2021-07-20 08:53:55 -07:00
RISCVInstrInfoC.td
RISCVInstrInfoD.td	[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno	2021-07-06 11:43:22 -07:00
RISCVInstrInfoF.td	[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno	2021-07-06 11:43:22 -07:00
RISCVInstrInfoM.td
RISCVInstrInfoV.td
RISCVInstrInfoVPseudos.td	[RISCV] Use tail agnostic policy for fixed vector vwmacc(u).	2021-07-16 10:41:09 -07:00
RISCVInstrInfoVSDPatterns.td	[RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul.	2021-06-21 11:27:44 -07:00
RISCVInstrInfoVVLPatterns.td	[RISCV] Use tail agnostic policy for fixed vector vwmacc(u).	2021-07-16 10:41:09 -07:00
RISCVInstrInfoZfh.td	[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno	2021-07-06 11:43:22 -07:00
RISCVInstructionSelector.cpp
RISCVISelDAGToDAG.cpp	[RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)	2021-07-20 08:53:55 -07:00
RISCVISelDAGToDAG.h	[RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)	2021-07-20 08:53:55 -07:00
RISCVISelLowering.cpp	[SelectionDAG] Fix the representation of ISD::STEP_VECTOR.	2021-07-21 10:58:40 -07:00
RISCVISelLowering.h	[RISCV] Add support for matching vwmul(u) and vwmacc(u) from fixed vectors.	2021-07-06 10:24:31 -07:00
RISCVLegalizerInfo.cpp	[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one	2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp
RISCVMergeBaseOffset.cpp
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp	[RISCV] Reserve an emergency spill slot for any RVV spills	2021-06-03 10:44:34 +01:00
RISCVRegisterInfo.h
RISCVRegisterInfo.td	[RISCV] Make VLEN no greater than 65536	2021-07-17 12:47:46 +08:00
RISCVSchedRocket.td
RISCVSchedSiFive7.td
RISCVSchedule.td
RISCVScheduleB.td
RISCVSubtarget.cpp	[RISCV] Make VLEN no greater than 65536	2021-07-17 12:47:46 +08:00
RISCVSubtarget.h	[RISCV] Don't enable loop vectorizer interleaving if the V extension isn't enabled.	2021-06-07 10:20:59 -07:00
RISCVSystemOperands.td
RISCVTargetMachine.cpp
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp	[RISCV] Teach constant materialization that it can use zext.w at the end with Zba to reduce number of instructions.	2021-07-16 09:35:56 -07:00
RISCVTargetTransformInfo.h	[RISCV] Don't enable Interleaved Access Vectorization	2021-06-18 12:32:30 +08:00