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b5fde80c0e
For now, only add instruction definitions for basic ALU operations. Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later. Differential Revision: https://reviews.llvm.org/D23561 llvm-svn: 285769
91 lines
4.1 KiB
TableGen
91 lines
4.1 KiB
TableGen
//===-- RISCVRegisterInfo.td - RISC-V Register defs --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the RISC-V register file
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//===----------------------------------------------------------------------===//
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let Namespace = "RISCV" in {
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def sub_32 : SubRegIndex<32>;
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class RISCVReg32<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
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let HWEncoding{4-0} = Enc;
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let AltNames = alt;
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}
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// RISCV64 registers don't define an AsmName or AltName. If they specified
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// names aliasing the RISCVReg32 registers, the generation of the default
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// MatchRegisterName/MatchRegisterAltName would fail. When necessary,
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// RISCVAsmParser will need to convert a register number from a RISCVReg32
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// to the equivalent RISCVReg64.
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class RISCVReg64<RISCVReg32 subreg> : Register<""> {
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let HWEncoding{4-0} = subreg.HWEncoding{4-0};
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let SubRegs = [subreg];
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let SubRegIndices = [sub_32];
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}
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def ABIRegAltName : RegAltNameIndex;
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}
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// Integer registers
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let RegAltNameIndices = [ABIRegAltName] in {
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def X0_32 : RISCVReg32<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
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def X1_32 : RISCVReg32<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
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def X2_32 : RISCVReg32<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
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def X3_32 : RISCVReg32<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
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def X4_32 : RISCVReg32<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
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def X5_32 : RISCVReg32<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
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def X6_32 : RISCVReg32<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
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def X7_32 : RISCVReg32<7, "x7", ["t2"]>, DwarfRegNum<[7]>;
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def X8_32 : RISCVReg32<8, "x8", ["s0"]>, DwarfRegNum<[8]>;
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def X9_32 : RISCVReg32<9, "x9", ["s1"]>, DwarfRegNum<[9]>;
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def X10_32 : RISCVReg32<10,"x10", ["a0"]>, DwarfRegNum<[10]>;
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def X11_32 : RISCVReg32<11,"x11", ["a1"]>, DwarfRegNum<[11]>;
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def X12_32 : RISCVReg32<12,"x12", ["a2"]>, DwarfRegNum<[12]>;
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def X13_32 : RISCVReg32<13,"x13", ["a3"]>, DwarfRegNum<[13]>;
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def X14_32 : RISCVReg32<14,"x14", ["a4"]>, DwarfRegNum<[14]>;
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def X15_32 : RISCVReg32<15,"x15", ["a5"]>, DwarfRegNum<[15]>;
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def X16_32 : RISCVReg32<16,"x16", ["a6"]>, DwarfRegNum<[16]>;
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def X17_32 : RISCVReg32<17,"x17", ["a7"]>, DwarfRegNum<[17]>;
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def X18_32 : RISCVReg32<18,"x18", ["s2"]>, DwarfRegNum<[18]>;
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def X19_32 : RISCVReg32<19,"x19", ["s3"]>, DwarfRegNum<[19]>;
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def X20_32 : RISCVReg32<20,"x20", ["s4"]>, DwarfRegNum<[20]>;
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def X21_32 : RISCVReg32<21,"x21", ["s5"]>, DwarfRegNum<[21]>;
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def X22_32 : RISCVReg32<22,"x22", ["s6"]>, DwarfRegNum<[22]>;
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def X23_32 : RISCVReg32<23,"x23", ["s7"]>, DwarfRegNum<[23]>;
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def X24_32 : RISCVReg32<24,"x24", ["s8"]>, DwarfRegNum<[24]>;
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def X25_32 : RISCVReg32<25,"x25", ["s9"]>, DwarfRegNum<[25]>;
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def X26_32 : RISCVReg32<26,"x26", ["s10"]>, DwarfRegNum<[26]>;
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def X27_32 : RISCVReg32<27,"x27", ["s11"]>, DwarfRegNum<[27]>;
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def X28_32 : RISCVReg32<28,"x28", ["t3"]>, DwarfRegNum<[28]>;
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def X29_32 : RISCVReg32<29,"x29", ["t4"]>, DwarfRegNum<[29]>;
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def X30_32 : RISCVReg32<30,"x30", ["t5"]>, DwarfRegNum<[30]>;
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def X31_32 : RISCVReg32<31,"x31", ["t6"]>, DwarfRegNum<[31]>;
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}
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foreach Index = 0-31 in {
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def X#Index#_64 : RISCVReg64<!cast<RISCVReg32>("X"#Index#"_32")>, DwarfRegNum<[Index]>;
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}
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// We currently define separate register classes for the 32-bit and 64-bit
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// GPRs. Once variable-sized register classes
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// <http://lists.llvm.org/pipermail/llvm-dev/2016-September/105027.html> or
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// similar are implemented, we can just use one 'GPR' class for most
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// instruction definitions.
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// TODO: once codegen is implemented, registers should be listed in an order
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// reflecting the preferred register allocation sequence.
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def GPR : RegisterClass<"RISCV", [i32], 32, (add
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(sequence "X%u_32", 0, 31)
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)>;
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def GPR64 : RegisterClass<"RISCV", [i64], 64, (add
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(sequence "X%u_64", 0, 31)
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)>;
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