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60 lines
2.0 KiB
C++
60 lines
2.0 KiB
C++
//===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the "Instituto Nokia de Tecnologia" and
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// is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMInstrInfo.h"
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#include "ARM.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "ARMGenInstrInfo.inc"
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using namespace llvm;
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ARMInstrInfo::ARMInstrInfo()
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: TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])),
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RI(*this) {
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}
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const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
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return &ARM::IntRegsRegClass;
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}
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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///
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bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg) const {
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MachineOpCode oc = MI.getOpcode();
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switch (oc) {
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case ARM::MOV: {
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assert(MI.getNumOperands() == 4 &&
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MI.getOperand(0).isRegister() &&
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"Invalid ARM MOV instruction");
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const MachineOperand &Arg = MI.getOperand(1);
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const MachineOperand &Shift = MI.getOperand(2);
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if (Arg.isRegister() && Shift.isImmediate() && Shift.getImmedValue() == 0) {
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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return true;
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}
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}
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}
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return false;
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}
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void ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const std::vector<MachineOperand> &Cond)const{
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// Can only insert uncond branches so far.
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assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
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BuildMI(&MBB, get(ARM::b)).addMBB(TBB);
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}
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