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fe9adb9248
This patch corresponds to review: https://reviews.llvm.org/D23155 This patch removes the VSHRC register class (based on D20310) and adds exploitation of the Power9 sub-word integer loads into VSX registers as well as vector sign extensions. The new instructions are useful for a few purposes: Int to Fp conversions of 1 or 2-byte values loaded from memory Building vectors of 1 or 2-byte integers with values loaded from memory Storing individual 1 or 2-byte elements from integer vectors This patch implements all of those uses. llvm-svn: 283190
16 lines
727 B
LLVM
16 lines
727 B
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck \
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; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck \
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; RUN: -implicit-check-not vmrg -implicit-check-not=vperm %s
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define <16 x i8> @test(i32* %s, i32* %t) {
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entry:
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%0 = bitcast i32* %s to <4 x i8>*
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%1 = load <4 x i8>, <4 x i8>* %0, align 4
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%2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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ret <16 x i8> %2
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; CHECK-LABEL: test
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; CHECK: lxsiwax 34, 0, 3
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; CHECK: xxspltw 34, 34, 1
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}
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