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fe9adb9248
This patch corresponds to review: https://reviews.llvm.org/D23155 This patch removes the VSHRC register class (based on D20310) and adds exploitation of the Power9 sub-word integer loads into VSX registers as well as vector sign extensions. The new instructions are useful for a few purposes: Int to Fp conversions of 1 or 2-byte values loaded from memory Building vectors of 1 or 2-byte integers with values loaded from memory Storing individual 1 or 2-byte elements from integer vectors This patch implements all of those uses. llvm-svn: 283190
54 lines
1.5 KiB
LLVM
54 lines
1.5 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck -check-prefix=CHECK-REG %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Unaligned loads/stores on P8 and later should use VSX where possible.
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define <2 x double> @test28u(<2 x double>* %a) {
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%v = load <2 x double>, <2 x double>* %a, align 8
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ret <2 x double> %v
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; CHECK-LABEL: @test28u
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; CHECK: lxvd2x 34, 0, 3
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; CHECK: blr
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}
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define void @test29u(<2 x double>* %a, <2 x double> %b) {
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store <2 x double> %b, <2 x double>* %a, align 8
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ret void
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; CHECK-LABEL: @test29u
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; CHECK: stxvd2x 34, 0, 3
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; CHECK: blr
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}
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define <4 x float> @test32u(<4 x float>* %a) {
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%v = load <4 x float>, <4 x float>* %a, align 8
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ret <4 x float> %v
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; CHECK-REG-LABEL: @test32u
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; CHECK-REG: lxvw4x 34, 0, 3
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test32u
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; CHECK-FISL: lxvw4x 34, 0, 3
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; CHECK-FISL: blr
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}
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define void @test33u(<4 x float>* %a, <4 x float> %b) {
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store <4 x float> %b, <4 x float>* %a, align 8
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ret void
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; CHECK-REG-LABEL: @test33u
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; CHECK-REG: stxvw4x 34, 0, 3
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test33u
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; CHECK-FISL: stxvw4x 34, 0, 3
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; CHECK-FISL: blr
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}
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