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7ebfc5f86b
This patch corresponds to review: The newly added VSX D-Form (register + offset) memory ops target the upper half of the VSX register set. The existing ones target the lower half. In order to unify these and have the ability to target all the VSX registers using D-Form operations, this patch defines Pseudo-ops for the loads/stores which are expanded post-RA. The expansion then choses the correct opcode based on the register that was allocated for the operation. llvm-svn: 283212
148 lines
3.9 KiB
LLVM
148 lines
3.9 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P9
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@d = common global double 0.000000e+00, align 8
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@f = common global float 0.000000e+00, align 4
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@i = common global i32 0, align 4
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@ui = common global i32 0, align 4
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; Function Attrs: nounwind
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define void @dblToInt() #0 {
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entry:
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%ii = alloca i32, align 4
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%0 = load double, double* @d, align 8
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%conv = fptosi double %0 to i32
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store volatile i32 %conv, i32* %ii, align 4
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ret void
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; CHECK-LABEL: @dblToInt
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; CHECK: xscvdpsxws [[REGCONV1:[0-9]+]],
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; CHECK: stxsiwx [[REGCONV1]],
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}
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; Function Attrs: nounwind
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define void @fltToInt() #0 {
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entry:
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%ii = alloca i32, align 4
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%0 = load float, float* @f, align 4
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%conv = fptosi float %0 to i32
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store volatile i32 %conv, i32* %ii, align 4
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ret void
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; CHECK-LABEL: @fltToInt
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; CHECK: xscvdpsxws [[REGCONV2:[0-9]+]],
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; CHECK: stxsiwx [[REGCONV2]],
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}
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; Function Attrs: nounwind
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define void @intToDbl() #0 {
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entry:
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%dd = alloca double, align 8
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%0 = load i32, i32* @i, align 4
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%conv = sitofp i32 %0 to double
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store volatile double %conv, double* %dd, align 8
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ret void
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; CHECK-LABEL: @intToDbl
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; CHECK: lxsiwax [[REGLD1:[0-9]+]],
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; CHECK: xscvsxddp {{[0-9]+}}, [[REGLD1]]
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}
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; Function Attrs: nounwind
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define void @intToFlt() #0 {
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entry:
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%ff = alloca float, align 4
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%0 = load i32, i32* @i, align 4
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%conv = sitofp i32 %0 to float
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store volatile float %conv, float* %ff, align 4
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ret void
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; CHECK-LABEL: @intToFlt
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; CHECK: lxsiwax [[REGLD2:[0-9]+]],
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; CHECK: xscvsxdsp {{[0-9]}}, [[REGLD2]]
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}
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; Function Attrs: nounwind
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define void @dblToUInt() #0 {
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entry:
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%uiui = alloca i32, align 4
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%0 = load double, double* @d, align 8
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%conv = fptoui double %0 to i32
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store volatile i32 %conv, i32* %uiui, align 4
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ret void
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; CHECK-LABEL: @dblToUInt
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; CHECK: xscvdpuxws [[REGCONV3:[0-9]+]],
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; CHECK: stxsiwx [[REGCONV3]],
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}
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; Function Attrs: nounwind
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define void @fltToUInt() #0 {
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entry:
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%uiui = alloca i32, align 4
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%0 = load float, float* @f, align 4
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%conv = fptoui float %0 to i32
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store volatile i32 %conv, i32* %uiui, align 4
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ret void
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; CHECK-LABEL: @fltToUInt
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; CHECK: xscvdpuxws [[REGCONV4:[0-9]+]],
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; CHECK: stxsiwx [[REGCONV4]],
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}
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; Function Attrs: nounwind
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define void @uIntToDbl() #0 {
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entry:
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%dd = alloca double, align 8
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%0 = load i32, i32* @ui, align 4
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%conv = uitofp i32 %0 to double
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store volatile double %conv, double* %dd, align 8
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ret void
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; CHECK-LABEL: @uIntToDbl
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; CHECK: lxsiwzx [[REGLD3:[0-9]+]],
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; CHECK: xscvuxddp {{[0-9]+}}, [[REGLD3]]
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}
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; Function Attrs: nounwind
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define void @uIntToFlt() #0 {
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entry:
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%ff = alloca float, align 4
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%0 = load i32, i32* @ui, align 4
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%conv = uitofp i32 %0 to float
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store volatile float %conv, float* %ff, align 4
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ret void
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; CHECK-LABEL: @uIntToFlt
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; CHECK: lxsiwzx [[REGLD4:[0-9]+]],
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; CHECK: xscvuxdsp {{[0-9]+}}, [[REGLD4]]
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}
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; Function Attrs: nounwind
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define void @dblToFloat() #0 {
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entry:
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%ff = alloca float, align 4
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%0 = load double, double* @d, align 8
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%conv = fptrunc double %0 to float
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store volatile float %conv, float* %ff, align 4
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ret void
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; CHECK-LABEL: @dblToFloat
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; CHECK: lxsdx [[REGLD5:[0-9]+]],
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; CHECK: stxsspx [[REGLD5]],
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; CHECK-P9-LABEL: @dblToFloat
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; CHECK-P9: lfd [[REGLD5:[0-9]+]],
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; CHECK-P9: stfs [[REGLD5]],
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}
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; Function Attrs: nounwind
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define void @floatToDbl() #0 {
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entry:
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%dd = alloca double, align 8
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%0 = load float, float* @f, align 4
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%conv = fpext float %0 to double
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store volatile double %conv, double* %dd, align 8
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ret void
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; CHECK-LABEL: @floatToDbl
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; CHECK: lxsspx [[REGLD5:[0-9]+]],
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; CHECK: stxsdx [[REGLD5]],
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; CHECK-P9-LABEL: @floatToDbl
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; CHECK-P9: lfs [[REGLD5:[0-9]+]],
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; CHECK-P9: stfd [[REGLD5]],
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}
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