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Mirror of https://github.com/RPCS3/llvm-mirror
c9513096a1
Given that INSERT_VECTOR_ELT operates on D registers anyway, combining 64-bit vectors into a 128-bit vector is basically free. Therefore, try to split BUILD_VECTOR nodes before giving up and lowering them to a series of INSERT_VECTOR_ELT instructions. Sometimes this allows dramatically better lowerings; see testcases for examples. Inspired by similar code in the x86 backend for AVX. Differential Revision: https://reviews.llvm.org/D27624 llvm-svn: 289706 |
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utils | ||
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LICENSE.TXT | ||
llvm.spec.in | ||
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RELEASE_TESTERS.TXT |
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