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1652ed61e6
I have added a new file: llvm/test/CodeGen/AArch64/README that describes what to do in the event one of the SVE codegen tests fails the warnings check. In addition, I've added comments to all the relevant SVE tests pointing users at the README file. Differential Revision: https://reviews.llvm.org/D83467
133 lines
4.9 KiB
LLVM
133 lines
4.9 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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;
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; SVE Logical Vector Immediate Unpredicated CodeGen
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;
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; ORR
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define <vscale x 16 x i8> @orr_i8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: orr_i8:
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; CHECK: orr z0.b, z0.b, #0xf
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; CHECK-NEXT: ret
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%elt = insertelement <vscale x 16 x i8> undef, i8 15, i32 0
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%splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
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%res = or <vscale x 16 x i8> %a, %splat
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @orr_i16(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: orr_i16:
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; CHECK: orr z0.h, z0.h, #0xfc07
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; CHECK-NEXT: ret
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%elt = insertelement <vscale x 8 x i16> undef, i16 64519, i32 0
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%splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
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%res = or <vscale x 8 x i16> %a, %splat
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @orr_i32(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: orr_i32:
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; CHECK: orr z0.s, z0.s, #0xffff00
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; CHECK-NEXT: ret
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%elt = insertelement <vscale x 4 x i32> undef, i32 16776960, i32 0
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%splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
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%res = or <vscale x 4 x i32> %a, %splat
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @orr_i64(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: orr_i64:
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; CHECK: orr z0.d, z0.d, #0xfffc000000000000
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; CHECK-NEXT: ret
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%elt = insertelement <vscale x 2 x i64> undef, i64 18445618173802708992, i32 0
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%splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
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%res = or <vscale x 2 x i64> %a, %splat
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ret <vscale x 2 x i64> %res
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}
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; EOR
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define <vscale x 16 x i8> @eor_i8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: eor_i8:
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; CHECK: eor z0.b, z0.b, #0xf
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; CHECK-NEXT: ret
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%elt = insertelement <vscale x 16 x i8> undef, i8 15, i32 0
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%splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
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%res = xor <vscale x 16 x i8> %a, %splat
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @eor_i16(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: eor_i16:
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; CHECK: eor z0.h, z0.h, #0xfc07
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; CHECK-NEXT: ret
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%elt = insertelement <vscale x 8 x i16> undef, i16 64519, i32 0
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%splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
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%res = xor <vscale x 8 x i16> %a, %splat
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @eor_i32(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: eor_i32:
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; CHECK: eor z0.s, z0.s, #0xffff00
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; CHECK-NEXT: ret
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%elt = insertelement <vscale x 4 x i32> undef, i32 16776960, i32 0
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%splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
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%res = xor <vscale x 4 x i32> %a, %splat
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @eor_i64(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: eor_i64:
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; CHECK: eor z0.d, z0.d, #0xfffc000000000000
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; CHECK-NEXT: ret
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%elt = insertelement <vscale x 2 x i64> undef, i64 18445618173802708992, i32 0
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%splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
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%res = xor <vscale x 2 x i64> %a, %splat
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ret <vscale x 2 x i64> %res
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}
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; AND
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define <vscale x 16 x i8> @and_i8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: and_i8:
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; CHECK: and z0.b, z0.b, #0xf
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; CHECK-NEXT: ret
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%elt = insertelement <vscale x 16 x i8> undef, i8 15, i32 0
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%splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
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%res = and <vscale x 16 x i8> %a, %splat
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @and_i16(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: and_i16:
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; CHECK: and z0.h, z0.h, #0xfc07
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; CHECK-NEXT: ret
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%elt = insertelement <vscale x 8 x i16> undef, i16 64519, i32 0
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%splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
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%res = and <vscale x 8 x i16> %a, %splat
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @and_i32(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: and_i32:
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; CHECK: and z0.s, z0.s, #0xffff00
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; CHECK-NEXT: ret
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%elt = insertelement <vscale x 4 x i32> undef, i32 16776960, i32 0
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%splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
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%res = and <vscale x 4 x i32> %a, %splat
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @and_i64(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: and_i64:
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; CHECK: and z0.d, z0.d, #0xfffc000000000000
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; CHECK-NEXT: ret
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%elt = insertelement <vscale x 2 x i64> undef, i64 18445618173802708992, i32 0
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%splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
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%res = and <vscale x 2 x i64> %a, %splat
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ret <vscale x 2 x i64> %res
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}
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