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llvm-mirror/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
Matt Arsenault 53cca02b90 GlobalISel: Verify G_BITCAST changes the type
Updated the AArch64 tests the best I could with my vague, inferred
understanding of AArch64 register banks. As far as I can tell, there
is only one 32-bit/64-bit type which will use the gpr register bank,
so we have to use the fpr bank for the other operand.
2020-07-08 17:16:27 -04:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: bitcast_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: bitcast_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[BITCAST:%[0-9]+]]:sgpr(<2 x s16>) = G_BITCAST [[COPY]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(<2 x s16>) = G_BITCAST %0
...
---
name: bitcast_v
legalized: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: bitcast_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[BITCAST:%[0-9]+]]:vgpr(<2 x s16>) = G_BITCAST [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<2 x s16>) = G_BITCAST %0
...