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53cca02b90
Updated the AArch64 tests the best I could with my vague, inferred understanding of AArch64 register banks. As far as I can tell, there is only one 32-bit/64-bit type which will use the gpr register bank, so we have to use the fpr bank for the other operand.
32 lines
940 B
YAML
32 lines
940 B
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
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---
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name: bitcast_s
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: bitcast_s
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[BITCAST:%[0-9]+]]:sgpr(<2 x s16>) = G_BITCAST [[COPY]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(<2 x s16>) = G_BITCAST %0
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...
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---
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name: bitcast_v
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: bitcast_v
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[BITCAST:%[0-9]+]]:vgpr(<2 x s16>) = G_BITCAST [[COPY]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(<2 x s16>) = G_BITCAST %0
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...
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