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llvm-mirror/test/CodeGen/AMDGPU/collapse-endcf-broken.mir
Matt Arsenault ec34fe0ec4 AMDGPU: Add additional MIR tests for exec mask optimizations
Also includes one example of how this transform is unsound. This isn't
verifying the copies are used in the control flow intrinisic patterns.

Also add option to disable exec mask opt pass. Since this pass is
unsound, it may be useful to turn it off until it is fixed.

llvm-svn: 357091
2019-03-27 16:58:30 +00:00

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1.6 KiB
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GXN %s
# FIXME: This is a miscompile, and the s_or_b64s need to be preserved.
---
name: invalid_end_cf_fold_0
tracksRegLiveness: true
liveins:
- { reg: '$vgpr0', virtual-reg: '%0' }
- { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
machineFunctionInfo:
isEntryFunction: true
body: |
; GXN-LABEL: name: invalid_end_cf_fold_0
; GXN: bb.0:
; GXN: successors: %bb.1(0x80000000)
; GXN: liveins: $vgpr0, $sgpr0_sgpr1
; GXN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
; GXN: $exec = S_OR_B64 $exec, [[COPY]], implicit-def $scc
; GXN: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $exec
; GXN: bb.1:
; GXN: successors: %bb.2(0x80000000)
; GXN: bb.2:
; GXN: $exec = S_OR_B64 $exec, [[COPY1]], implicit-def $scc
; GXN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GXN: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GXN: DS_WRITE_B32 [[DEF]], [[DEF1]], 0, 0, implicit $m0, implicit $exec :: (store 4, addrspace 3)
; GXN: S_ENDPGM 0
bb.0:
liveins: $vgpr0, $sgpr0_sgpr1
%0:sgpr_64 = COPY $sgpr0_sgpr1
%1:sgpr_64 = COPY $exec
$exec = S_OR_B64 $exec, %0, implicit-def $scc
%2:sgpr_64 = COPY $exec
bb.1:
$exec = S_OR_B64 $exec, %1, implicit-def $scc
bb.2:
$exec = S_OR_B64 $exec, %2, implicit-def $scc
%5:vgpr_32 = IMPLICIT_DEF
%6:vgpr_32 = IMPLICIT_DEF
DS_WRITE_B32 %5, %6, 0, 0, implicit $m0, implicit $exec :: (store 4, addrspace 3)
S_ENDPGM 0
...