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b1879e506b
Based on D72931 This adds a new feature called A16 which is enabled for gfx10. gfx9 keeps the R128A16 feature so it can share all the instruction encodings with gfx7/8. Differential Revision: https://reviews.llvm.org/D73956
239 lines
10 KiB
LLVM
239 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
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define amdgpu_ps void @store_f16_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
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; GFX9-LABEL: store_f16_1d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x1 unorm a16 d16
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: store_f16_1d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm a16 d16
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; GFX10-NEXT: s_endpgm
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%bitcast = bitcast <2 x i32> %val to <4 x half>
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call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @store_v2f16_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
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; GFX9-LABEL: store_v2f16_1d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x3 unorm a16 d16
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: store_v2f16_1d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm a16 d16
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; GFX10-NEXT: s_endpgm
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%bitcast = bitcast <2 x i32> %val to <4 x half>
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call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @store_v3f16_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
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; GFX9-LABEL: store_v3f16_1d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x7 unorm a16 d16
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: store_v3f16_1d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm a16 d16
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; GFX10-NEXT: s_endpgm
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%bitcast = bitcast <2 x i32> %val to <4 x half>
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call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @store_v4f16_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
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; GFX9-LABEL: store_v4f16_1d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_store v[1:2], v0, s[0:7] dmask:0xf unorm a16 d16
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: store_v4f16_1d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: image_store v[1:2], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm a16 d16
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; GFX10-NEXT: s_endpgm
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%bitcast = bitcast <2 x i32> %val to <4 x half>
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call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @store_f16_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
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; GFX9-LABEL: store_f16_2d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x1 unorm a16 d16
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: store_f16_2d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm a16 d16
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; GFX10-NEXT: s_endpgm
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%y = extractelement <2 x i16> %coords, i32 1
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%bitcast = bitcast <2 x i32> %val to <4 x half>
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call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @store_v2f16_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
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; GFX9-LABEL: store_v2f16_2d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x3 unorm a16 d16
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: store_v2f16_2d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm a16 d16
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; GFX10-NEXT: s_endpgm
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%y = extractelement <2 x i16> %coords, i32 1
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%bitcast = bitcast <2 x i32> %val to <4 x half>
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call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @store_v3f16_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
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; GFX9-LABEL: store_v3f16_2d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x7 unorm a16 d16
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: store_v3f16_2d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: image_store v[1:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D unorm a16 d16
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; GFX10-NEXT: s_endpgm
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%y = extractelement <2 x i16> %coords, i32 1
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%bitcast = bitcast <2 x i32> %val to <4 x half>
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call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @store_v4f16_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
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; GFX9-LABEL: store_v4f16_2d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_store v[1:2], v0, s[0:7] dmask:0xf unorm a16 d16
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: store_v4f16_2d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: image_store v[1:2], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm a16 d16
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; GFX10-NEXT: s_endpgm
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main_body:
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%x = extractelement <2 x i16> %coords, i32 0
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%y = extractelement <2 x i16> %coords, i32 1
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%bitcast = bitcast <2 x i32> %val to <4 x half>
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call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 15, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @store_f16_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) {
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; GFX9-LABEL: store_f16_3d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0x1 unorm a16 d16
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: store_f16_3d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm a16 d16
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; GFX10-NEXT: s_endpgm
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main_body:
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%x = extractelement <2 x i16> %coords_lo, i32 0
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%y = extractelement <2 x i16> %coords_lo, i32 1
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%z = extractelement <2 x i16> %coords_hi, i32 0
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%bitcast = bitcast <2 x i32> %val to <4 x half>
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call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 1, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @store_v2f16_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) {
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; GFX9-LABEL: store_v2f16_3d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0x3 unorm a16 d16
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: store_v2f16_3d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm a16 d16
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; GFX10-NEXT: s_endpgm
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main_body:
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%x = extractelement <2 x i16> %coords_lo, i32 0
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%y = extractelement <2 x i16> %coords_lo, i32 1
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%z = extractelement <2 x i16> %coords_hi, i32 0
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%bitcast = bitcast <2 x i32> %val to <4 x half>
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call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 3, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @store_v3f16_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) {
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; GFX9-LABEL: store_v3f16_3d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0x7 unorm a16 d16
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: store_v3f16_3d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_3D unorm a16 d16
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; GFX10-NEXT: s_endpgm
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main_body:
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%x = extractelement <2 x i16> %coords_lo, i32 0
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%y = extractelement <2 x i16> %coords_lo, i32 1
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%z = extractelement <2 x i16> %coords_hi, i32 0
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%bitcast = bitcast <2 x i32> %val to <4 x half>
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call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 7, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @store_v4f16_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) {
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; GFX9-LABEL: store_v4f16_3d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0xf unorm a16 d16
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: store_v4f16_3d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 d16
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; GFX10-NEXT: s_endpgm
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main_body:
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%x = extractelement <2 x i16> %coords_lo, i32 0
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%y = extractelement <2 x i16> %coords_lo, i32 1
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%z = extractelement <2 x i16> %coords_hi, i32 0
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%bitcast = bitcast <2 x i32> %val to <4 x half>
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call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 15, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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declare void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half>, i32, i16, <8 x i32>, i32, i32) #2
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declare void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half>, i32, i16, i16, <8 x i32>, i32, i32) #2
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declare void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half>, i32, i16, i16, i16, <8 x i32>, i32, i32) #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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