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711582147b
This adds the FPC (floating-point control register) as a reserved physical register and models its use by SystemZ instructions. Note that only the current rounding modes and the IEEE exception masks are modeled. *Changes* of the FPC due to exceptions (in particular the IEEE exception flags and the DXC) are not modeled. At this point, this patch is mostly NFC, but it will prevent scheduling of floating-point instructions across SPFC/LFPC etc. llvm-svn: 360570
45 lines
1.1 KiB
YAML
45 lines
1.1 KiB
YAML
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z10 -no-integrated-as -start-after=block-placement %s -o - | FileCheck %s
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# Test that LTEBR is used without an unnecessary LER
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--- |
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define float @f15(float %val, float %dummy, float* %dest) {
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entry:
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call void asm sideeffect "blah $0", "{f2}"(float %val)
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%cmp = fcmp olt float %val, 0.000000e+00
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br i1 %cmp, label %exit, label %store
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store: ; preds = %entry
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store float %val, float* %dest
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br label %exit
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exit: ; preds = %store, %entry
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ret float %val
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}
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...
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# CHECK: ltebr %f2, %f0
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---
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name: f15
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tracksRegLiveness: true
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liveins:
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- { reg: '$f0s', virtual-reg: '' }
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- { reg: '$r2d', virtual-reg: '' }
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body: |
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bb.0.entry:
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liveins: $f0s, $r2d
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LTEBRCompare $f0s, $f0s, implicit-def $cc, implicit $fpc
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$f2s = LER $f0s
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INLINEASM &"blah $0", 1, 9, $f2s
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CondReturn 15, 4, implicit $f0s, implicit $cc
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bb.1.store:
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liveins: $f0s, $r2d
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STE $f0s, killed $r2d, 0, $noreg :: (store 4 into %ir.dest)
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Return implicit $f0s
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...
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