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f2d9f44d91
When splitting a subrange we end up with two different subranges covering two different, non overlapping, lanes. As part of this splitting the VNIs of the original live-range need to be dispatched to the subranges according to which lanes they are actually defining. Prior to this patch we were assuming that all values were defining all lanes. This was wrong as demonstrated by llvm.org/PR40835. Differential Revision: https://reviews.llvm.org/D59731 llvm-svn: 357032
95 lines
3.6 KiB
YAML
95 lines
3.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple s390x-ibm-linux -mcpu=z13 -systemz-subreg-liveness -verify-machineinstrs -start-before simple-register-coalescing -stop-after greedy -o - %s | FileCheck %s
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# Check that when we split the live-range with several active lanes
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# as part of the live-range update, we correctly eliminate the VNI from
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# the relevant part.
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#
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# In this specific test, the register coalescer will:
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# 1. Merge %0 with %1, creating a live-range for the full value subreg_l32 + subreg_h32
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# (actually %0 gets merge with %1 via rematerialization, and technically %0 and %1
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# remain two different live-ranges.)
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# 2. Merge %2 with %1 triggering a split into the subreg_l32 + subreg_h32 ranges, since
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# %2 only touches subreg_l32. As part of the split the subrange covering subreg_h32
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# must contain only the VNI for the high part (i.e., the one tied with the remaaat of %0).
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# This used to be broken and trigger a machine verifier error, because we were not
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# clearing the dead value w.r.t. lanes when doing the splitting. I.e., we were ending
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# with a subrange referring a value that did not define that lane.
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#
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# PR40835
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---
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name: main
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: main
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; CHECK: [[LGHI:%[0-9]+]]:gr64bit = LGHI 43
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; CHECK: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 43
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; CHECK: [[LGHI1]].subreg_l32:gr64bit = MSR [[LGHI1]].subreg_l32, [[LGHI1]].subreg_l32
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; CHECK: [[LGHI1]].subreg_l32:gr64bit = AHIMux [[LGHI1]].subreg_l32, 9, implicit-def dead $cc
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; CHECK: undef %3.subreg_l64:gr128bit = LGFI -245143785, implicit [[LGHI1]].subreg_l32
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; CHECK: [[DLGR:%[0-9]+]]:gr128bit = DLGR [[DLGR]], [[LGHI]]
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; CHECK: Return implicit [[DLGR]]
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%0:gr64bit = LGHI 43
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%1:gr32bit = COPY %0.subreg_l32
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%1:gr32bit = MSR %1, %1
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%2:gr32bit = COPY killed %1
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%2:gr32bit = AHIMux killed %2, 9, implicit-def dead $cc
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undef %3.subreg_l64:gr128bit = LGFI -245143785, implicit killed %2
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%3:gr128bit = DLGR %3:gr128bit, killed %0
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Return implicit killed %3
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...
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# Make sure the compiler does not choke on VNIs that don't
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# an explicit MI as definition.
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# In that specific example, this is the PHI not explicitly
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# represented for the value carried by %7.
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---
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name: segfault
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tracksRegLiveness: true
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liveins: []
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body: |
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; CHECK-LABEL: name: segfault
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: [[LGHI:%[0-9]+]]:addr64bit = LGHI 0
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; CHECK: bb.1:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: ADJCALLSTACKDOWN 0, 0
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; CHECK: [[LGFR:%[0-9]+]]:gr64bit = LGFR [[LGHI]].subreg_l32
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; CHECK: $r2d = LGHI 123
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; CHECK: $r3d = LGHI 0
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; CHECK: $r4d = LGHI 0
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; CHECK: $r5d = COPY [[LGFR]]
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; CHECK: KILL killed $r2d, killed $r3d, killed $r4d, $r5d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc
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; CHECK: ADJCALLSTACKUP 0, 0
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; CHECK: [[LGHI]]:addr64bit = nuw nsw LA [[LGHI]], 1, $noreg
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; CHECK: J %bb.1
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bb.0:
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successors: %bb.1(0x80000000)
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%2:gr64bit = LGHI 0
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%5:gr64bit = LGHI 123
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%7:addr64bit = COPY %2
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bb.1:
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successors: %bb.1(0x80000000)
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%0:addr64bit = COPY killed %7
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ADJCALLSTACKDOWN 0, 0
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%3:gr32bit = COPY %0.subreg_l32
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%4:gr64bit = LGFR killed %3
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$r2d = COPY %5
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$r3d = COPY %2
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$r4d = COPY %2
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$r5d = COPY killed %4
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KILL killed $r2d, killed $r3d, killed $r4d, killed $r5d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc
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ADJCALLSTACKUP 0, 0
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%1:gr64bit = nuw nsw LA killed %0, 1, $noreg
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%7:addr64bit = COPY killed %1
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J %bb.1
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...
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