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26169930ef
Summary: Change VEAsmParser to support identification with relocation information in assmebler. Change VEAsmBackend to support relocation information in MC layer. Change VEDisassembler and VEMCCodeEmitter to support binary generation of branch target operands. Add REFLONG fixup and variant kind to support new R_VE_REFLONG ELF symbol. And, add regression test in both MC and CodeGen to check binary genaration with relocation information. Differential Revision: https://reviews.llvm.org/D81553
31 lines
908 B
LLVM
31 lines
908 B
LLVM
; RUN: llc -filetype=obj -mtriple=ve -o - %s | llvm-objdump - -d -r \
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; RUN: | FileCheck %s
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; RUN: llc -filetype=obj -mtriple=ve -relocation-model=pic -o - %s \
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; RUN: | llvm-objdump - -d -r | FileCheck %s -check-prefix=PIC
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; CHECK: lea %s0, 0
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; CHECK-NEXT: R_VE_LO32 foo
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea.sl %s12, (, %s0)
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; CHECK-NEXT: R_VE_HI32 foo
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; PIC: lea %s15, (-24)
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; PIC-NEXT: R_VE_PC_LO32 _GLOBAL_OFFSET_TABLE_
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; PIC-NEXT: and %s15, %s15, (32)0
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; PIC-NEXT: sic %s16
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; PIC-NEXT: lea.sl %s15, (%s16, %s15)
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; PIC-NEXT: R_VE_PC_HI32 _GLOBAL_OFFSET_TABLE_
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; PIC-NEXT: lea %s12, (-24)
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; PIC-NEXT: R_VE_PLT_LO32 foo
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; PIC-NEXT: and %s12, %s12, (32)0
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; PIC-NEXT: sic %s16
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; PIC-NEXT: lea.sl %s12, (%s16, %s12)
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; PIC-NEXT: R_VE_PLT_HI32 foo
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define i32 @main() {
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entry:
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%call = call i32 @foo()
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ret i32 %call
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}
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declare i32 @foo()
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