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bb4ad38d95
VE has only 64 bits AND/OR/XOR instructions. We pretended that VE has 32 bits instructions also, but doing it increase the number of generated instructions. Therefore, we decide to promote 32 bits operations and use only 64 bits instructions in back end. We also avoid pretending that VE has 32 bits LEA instruction. Update regression tests also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D85726
160 lines
3.8 KiB
LLVM
160 lines
3.8 KiB
LLVM
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
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define signext i8 @func8s(i8 signext %a, i8 signext %b) {
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; CHECK-LABEL: func8s:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i8 %a, %b
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ret i8 %res
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}
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define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
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; CHECK-LABEL: func8z:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, %s1, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i8 %b, %a
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ret i8 %res
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}
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define signext i8 @funci8s(i8 signext %a) {
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; CHECK-LABEL: funci8s:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, 5, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i8 %a, 5
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ret i8 %res
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}
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define zeroext i8 @funci8z(i8 zeroext %a) {
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; CHECK-LABEL: funci8z:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s1, 251
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; CHECK-NEXT: xor %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i8 -5, %a
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ret i8 %res
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}
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define signext i16 @func16s(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: func16s:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i16 %a, %b
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ret i16 %res
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}
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define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: func16z:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, %s1, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i16 %b, %a
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ret i16 %res
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}
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define signext i16 @funci16s(i16 signext %a) {
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; CHECK-LABEL: funci16s:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, -1, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i16 %a, 65535
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ret i16 %res
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}
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define zeroext i16 @funci16z(i16 zeroext %a) {
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; CHECK-LABEL: funci16z:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, %s0, (52)0
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i16 4095, %a
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ret i16 %res
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}
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define signext i32 @func32s(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: func32s:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i32 %a, %b
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ret i32 %res
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}
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define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: func32z:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i32 %a, %b
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ret i32 %res
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}
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define signext i32 @funci32s(i32 signext %a) {
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; CHECK-LABEL: funci32s:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, %s0, (36)0
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i32 %a, 268435455
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ret i32 %res
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}
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define zeroext i32 @funci32z(i32 zeroext %a) {
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; CHECK-LABEL: funci32z:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, %s0, (36)0
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i32 %a, 268435455
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ret i32 %res
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}
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define i32 @funci32_another(i32 %0) {
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; CHECK-LABEL: funci32_another:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: lea %s1, -2147483648
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: xor %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = xor i32 %0, -2147483648
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ret i32 %2
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}
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define i64 @func64(i64 %a, i64 %b) {
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; CHECK-LABEL: func64:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, %s0, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i64 %a, %b
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ret i64 %res
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}
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define i64 @func64i(i64 %a) {
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; CHECK-LABEL: func64i:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, %s0, (24)0
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i64 %a, 1099511627775
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ret i64 %res
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}
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define i128 @func128(i128 %a, i128 %b) {
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; CHECK-LABEL: func128:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, %s2, %s0
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; CHECK-NEXT: xor %s1, %s3, %s1
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i128 %b, %a
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ret i128 %res
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}
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define i128 @funci128(i128 %a) {
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; CHECK-LABEL: funci128:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, 5, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%res = xor i128 %a, 5
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ret i128 %res
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}
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