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2e8c69fd7b
This should fix: https://llvm.org/bugs/show_bug.cgi?id=30433 There are a couple of open questions about the codegen: 1. Should we let scalar ops be scalars and avoid vector constant loads/splats? 2. Should we have a pass to combine constants such as the inverted pair that we have here? Differential Revision: https://reviews.llvm.org/D25165 llvm-svn: 283119
170 lines
5.4 KiB
LLVM
170 lines
5.4 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-macosx10.10.0 -mattr=+sse2 | FileCheck %s --check-prefix=SSE2 --check-prefix=CHECK
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; RUN: llc < %s -mtriple=x86_64-apple-macosx10.10.0 -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=CHECK
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; Assertions have been enhanced from utils/update_test_checks.py to show the constant pool values.
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; Use a macosx triple to make sure the format of those constant strings is exact.
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; CHECK: [[SIGNMASK1:L.+]]:
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; CHECK-NEXT: .long 2147483648
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; CHECK-NEXT: .long 2147483648
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; CHECK-NEXT: .long 2147483648
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; CHECK-NEXT: .long 2147483648
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; CHECK: [[MAGMASK1:L.+]]:
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; CHECK-NEXT: .long 2147483647
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; CHECK-NEXT: .long 2147483647
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; CHECK-NEXT: .long 2147483647
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; CHECK-NEXT: .long 2147483647
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define <4 x float> @v4f32(<4 x float> %a, <4 x float> %b) nounwind {
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; SSE2-LABEL: v4f32:
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; SSE2: # BB#0:
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; SSE2-NEXT: andps [[SIGNMASK1]](%rip), %xmm1
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; SSE2-NEXT: andps [[MAGMASK1]](%rip), %xmm0
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; SSE2-NEXT: orps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: v4f32:
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; AVX: # BB#0:
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; AVX-NEXT: vandps [[SIGNMASK1]](%rip), %xmm1, %xmm1
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; AVX-NEXT: vandps [[MAGMASK1]](%rip), %xmm0, %xmm0
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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%tmp = tail call <4 x float> @llvm.copysign.v4f32( <4 x float> %a, <4 x float> %b )
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ret <4 x float> %tmp
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}
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; SSE2: [[SIGNMASK2:L.+]]:
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; SSE2-NEXT: .long 2147483648
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; SSE2-NEXT: .long 2147483648
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; SSE2-NEXT: .long 2147483648
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; SSE2-NEXT: .long 2147483648
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; SSE2: [[MAGMASK2:L.+]]:
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; SSE2-NEXT: .long 2147483647
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; SSE2-NEXT: .long 2147483647
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; SSE2-NEXT: .long 2147483647
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; SSE2-NEXT: .long 2147483647
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; AVX: [[SIGNMASK2:L.+]]:
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; AVX-NEXT: .long 2147483648
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; AVX-NEXT: .long 2147483648
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; AVX-NEXT: .long 2147483648
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; AVX-NEXT: .long 2147483648
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; AVX-NEXT: .long 2147483648
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; AVX-NEXT: .long 2147483648
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; AVX-NEXT: .long 2147483648
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; AVX-NEXT: .long 2147483648
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; AVX: [[MAGMASK2:L.+]]:
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; AVX-NEXT: .long 2147483647
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; AVX-NEXT: .long 2147483647
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; AVX-NEXT: .long 2147483647
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; AVX-NEXT: .long 2147483647
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; AVX-NEXT: .long 2147483647
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; AVX-NEXT: .long 2147483647
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; AVX-NEXT: .long 2147483647
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; AVX-NEXT: .long 2147483647
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define <8 x float> @v8f32(<8 x float> %a, <8 x float> %b) nounwind {
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; SSE2-LABEL: v8f32:
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; SSE2: # BB#0:
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; SSE2-NEXT: movaps [[SIGNMASK2]](%rip), %xmm4
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; SSE2-NEXT: andps %xmm4, %xmm2
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; SSE2-NEXT: movaps [[MAGMASK2]](%rip), %xmm5
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; SSE2-NEXT: andps %xmm5, %xmm0
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; SSE2-NEXT: orps %xmm2, %xmm0
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; SSE2-NEXT: andps %xmm4, %xmm3
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; SSE2-NEXT: andps %xmm5, %xmm1
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; SSE2-NEXT: orps %xmm3, %xmm1
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: v8f32:
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; AVX: # BB#0:
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; AVX-NEXT: vandps [[SIGNMASK2]](%rip), %ymm1, %ymm1
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; AVX-NEXT: vandps [[MAGMASK2]](%rip), %ymm0, %ymm0
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; AVX-NEXT: vorps %ymm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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;
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%tmp = tail call <8 x float> @llvm.copysign.v8f32( <8 x float> %a, <8 x float> %b )
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ret <8 x float> %tmp
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}
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; CHECK: [[SIGNMASK3:L.+]]:
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; CHECK-NEXT: .quad -9223372036854775808
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; CHECK-NEXT: .quad -9223372036854775808
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; CHECK: [[MAGMASK3:L.+]]:
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; CHECK-NEXT: .quad 9223372036854775807
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; CHECK-NEXT: .quad 9223372036854775807
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define <2 x double> @v2f64(<2 x double> %a, <2 x double> %b) nounwind {
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; SSE2-LABEL: v2f64:
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; SSE2: # BB#0:
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; SSE2-NEXT: andps [[SIGNMASK3]](%rip), %xmm1
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; SSE2-NEXT: andps [[MAGMASK3]](%rip), %xmm0
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; SSE2-NEXT: orps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: v2f64:
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; AVX: # BB#0:
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; AVX-NEXT: vandps [[SIGNMASK3]](%rip), %xmm1, %xmm1
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; AVX-NEXT: vandps [[MAGMASK3]](%rip), %xmm0, %xmm0
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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%tmp = tail call <2 x double> @llvm.copysign.v2f64( <2 x double> %a, <2 x double> %b )
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ret <2 x double> %tmp
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}
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; SSE2: [[SIGNMASK4:L.+]]:
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; SSE2-NEXT: .quad -9223372036854775808
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; SSE2-NEXT: .quad -9223372036854775808
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; SSE2: [[MAGMASK4:L.+]]:
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; SSE2-NEXT: .quad 9223372036854775807
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; SSE2-NEXT: .quad 9223372036854775807
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; AVX: [[SIGNMASK4:L.+]]:
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; AVX-NEXT: .quad -9223372036854775808
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; AVX-NEXT: .quad -9223372036854775808
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; AVX-NEXT: .quad -9223372036854775808
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; AVX-NEXT: .quad -9223372036854775808
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; AVX: [[MAGMASK4:L.+]]:
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; AVX-NEXT: .quad 9223372036854775807
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; AVX-NEXT: .quad 9223372036854775807
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; AVX-NEXT: .quad 9223372036854775807
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; AVX-NEXT: .quad 9223372036854775807
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define <4 x double> @v4f64(<4 x double> %a, <4 x double> %b) nounwind {
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; SSE2-LABEL: v4f64:
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; SSE2: # BB#0:
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; SSE2-NEXT: movaps [[SIGNMASK4]](%rip), %xmm4
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; SSE2-NEXT: andps %xmm4, %xmm2
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; SSE2-NEXT: movaps [[MAGMASK4]](%rip), %xmm5
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; SSE2-NEXT: andps %xmm5, %xmm0
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; SSE2-NEXT: orps %xmm2, %xmm0
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; SSE2-NEXT: andps %xmm4, %xmm3
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; SSE2-NEXT: andps %xmm5, %xmm1
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; SSE2-NEXT: orps %xmm3, %xmm1
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: v4f64:
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; AVX: # BB#0:
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; AVX-NEXT: vandps [[SIGNMASK4]](%rip), %ymm1, %ymm1
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; AVX-NEXT: vandps [[MAGMASK4]](%rip), %ymm0, %ymm0
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; AVX-NEXT: vorps %ymm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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;
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%tmp = tail call <4 x double> @llvm.copysign.v4f64( <4 x double> %a, <4 x double> %b )
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ret <4 x double> %tmp
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}
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declare <4 x float> @llvm.copysign.v4f32(<4 x float> %Mag, <4 x float> %Sgn)
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declare <8 x float> @llvm.copysign.v8f32(<8 x float> %Mag, <8 x float> %Sgn)
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declare <2 x double> @llvm.copysign.v2f64(<2 x double> %Mag, <2 x double> %Sgn)
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declare <4 x double> @llvm.copysign.v4f64(<4 x double> %Mag, <4 x double> %Sgn)
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