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230 lines
7.4 KiB
LLVM
230 lines
7.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx2 | FileCheck %s --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx512f | FileCheck %s --check-prefix=AVX512
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; Verify that we don't scalarize a packed vector shift left of 16-bit
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; signed integers if the amount is a constant build_vector.
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; Check that we produce a SSE2 packed integer multiply (pmullw) instead.
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define <8 x i16> @test1(<8 x i16> %a) {
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; SSE-LABEL: test1:
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; SSE: # BB#0:
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; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: test1:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test1:
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; AVX512: # BB#0:
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; AVX512-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
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; AVX512-NEXT: retq
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%shl = shl <8 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
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ret <8 x i16> %shl
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}
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define <8 x i16> @test2(<8 x i16> %a) {
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; SSE-LABEL: test2:
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; SSE: # BB#0:
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; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: test2:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test2:
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; AVX512: # BB#0:
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; AVX512-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
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; AVX512-NEXT: retq
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%shl = shl <8 x i16> %a, <i16 0, i16 undef, i16 0, i16 0, i16 1, i16 undef, i16 -1, i16 1>
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ret <8 x i16> %shl
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}
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; Verify that a vector shift left of 32-bit signed integers is simply expanded
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; into a SSE4.1 pmulld (instead of cvttps2dq + pmulld) if the vector of shift
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; counts is a constant build_vector.
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define <4 x i32> @test3(<4 x i32> %a) {
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; SSE-LABEL: test3:
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; SSE: # BB#0:
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: test3:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test3:
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; AVX512: # BB#0:
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; AVX512-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX512-NEXT: retq
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%shl = shl <4 x i32> %a, <i32 1, i32 -1, i32 2, i32 -3>
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ret <4 x i32> %shl
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}
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define <4 x i32> @test4(<4 x i32> %a) {
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; SSE-LABEL: test4:
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; SSE: # BB#0:
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: test4:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test4:
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; AVX512: # BB#0:
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; AVX512-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX512-NEXT: retq
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%shl = shl <4 x i32> %a, <i32 0, i32 0, i32 1, i32 1>
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ret <4 x i32> %shl
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}
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; If we have AVX/SSE2 but not AVX2, verify that the following shift is split
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; into two pmullw instructions. With AVX2, the test case below would produce
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; a single vpmullw.
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define <16 x i16> @test5(<16 x i16> %a) {
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; SSE-LABEL: test5:
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; SSE: # BB#0:
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; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2,2,4,8,128,1,512,2048]
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; SSE-NEXT: pmullw %xmm2, %xmm0
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; SSE-NEXT: pmullw %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: test5:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test5:
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; AVX512: # BB#0:
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; AVX512-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
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; AVX512-NEXT: retq
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%shl = shl <16 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
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ret <16 x i16> %shl
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}
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; If we have AVX/SSE4.1 but not AVX2, verify that the following shift is split
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; into two pmulld instructions. With AVX2, the test case below would produce
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; a single vpsllvd instead.
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define <8 x i32> @test6(<8 x i32> %a) {
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; SSE-LABEL: test6:
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; SSE: # BB#0:
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; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2,2,4,8]
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; SSE-NEXT: pmulld %xmm2, %xmm0
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; SSE-NEXT: pmulld %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: test6:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test6:
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; AVX512: # BB#0:
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; AVX512-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0
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; AVX512-NEXT: retq
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%shl = shl <8 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
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ret <8 x i32> %shl
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}
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; With AVX2 and AVX512, the test case below should produce a sequence of
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; two vpmullw instructions. On SSE2 instead, we split the shift in four
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; parts and then we convert each part into a pmullw.
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define <32 x i16> @test7(<32 x i16> %a) {
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; SSE-LABEL: test7:
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; SSE: # BB#0:
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; SSE-NEXT: movdqa {{.*#+}} xmm4 = [2,2,4,8,128,1,512,2048]
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; SSE-NEXT: pmullw %xmm4, %xmm0
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; SSE-NEXT: pmullw %xmm4, %xmm1
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; SSE-NEXT: pmullw %xmm4, %xmm2
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; SSE-NEXT: pmullw %xmm4, %xmm3
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: test7:
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; AVX2: # BB#0:
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; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [2,2,4,8,128,1,512,2048,2,2,4,8,128,1,512,2048]
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; AVX2-NEXT: vpmullw %ymm2, %ymm0, %ymm0
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; AVX2-NEXT: vpmullw %ymm2, %ymm1, %ymm1
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test7:
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; AVX512: # BB#0:
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; AVX512-NEXT: vmovdqa {{.*#+}} ymm2 = [2,2,4,8,128,1,512,2048,2,2,4,8,128,1,512,2048]
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; AVX512-NEXT: vpmullw %ymm2, %ymm0, %ymm0
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; AVX512-NEXT: vpmullw %ymm2, %ymm1, %ymm1
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; AVX512-NEXT: retq
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%shl = shl <32 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
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ret <32 x i16> %shl
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}
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; Similar to test7; the difference is that with AVX512 support
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; we only produce a single vpsllvd/vpsllvq instead of a pair of vpsllvd/vpsllvq.
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define <16 x i32> @test8(<16 x i32> %a) {
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; SSE-LABEL: test8:
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; SSE: # BB#0:
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; SSE-NEXT: movdqa {{.*#+}} xmm4 = [2,2,4,8]
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; SSE-NEXT: pmulld %xmm4, %xmm0
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; SSE-NEXT: pmulld %xmm4, %xmm1
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; SSE-NEXT: pmulld %xmm4, %xmm2
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; SSE-NEXT: pmulld %xmm4, %xmm3
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: test8:
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; AVX2: # BB#0:
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; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [1,1,2,3,1,1,2,3]
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; AVX2-NEXT: vpsllvd %ymm2, %ymm0, %ymm0
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; AVX2-NEXT: vpsllvd %ymm2, %ymm1, %ymm1
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test8:
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; AVX512: # BB#0:
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; AVX512-NEXT: vpsllvd {{.*}}(%rip), %zmm0, %zmm0
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; AVX512-NEXT: retq
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%shl = shl <16 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
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ret <16 x i32> %shl
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}
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; The shift from 'test9' gets shifted separately and blended if we don't have AVX2/AVX512f support.
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define <8 x i64> @test9(<8 x i64> %a) {
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; SSE-LABEL: test9:
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; SSE: # BB#0:
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; SSE-NEXT: movdqa %xmm1, %xmm4
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; SSE-NEXT: psllq $3, %xmm4
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; SSE-NEXT: psllq $2, %xmm1
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm4[4,5,6,7]
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; SSE-NEXT: movdqa %xmm3, %xmm4
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; SSE-NEXT: psllq $3, %xmm4
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; SSE-NEXT: psllq $2, %xmm3
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; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm4[4,5,6,7]
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; SSE-NEXT: paddq %xmm0, %xmm0
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; SSE-NEXT: paddq %xmm2, %xmm2
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: test9:
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; AVX2: # BB#0:
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; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [1,1,2,3]
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; AVX2-NEXT: vpsllvq %ymm2, %ymm0, %ymm0
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; AVX2-NEXT: vpsllvq %ymm2, %ymm1, %ymm1
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test9:
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; AVX512: # BB#0:
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; AVX512-NEXT: vpsllvq {{.*}}(%rip), %zmm0, %zmm0
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; AVX512-NEXT: retq
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%shl = shl <8 x i64> %a, <i64 1, i64 1, i64 2, i64 3, i64 1, i64 1, i64 2, i64 3>
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ret <8 x i64> %shl
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}
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