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128 lines
4.1 KiB
LLVM
128 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64
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; test vector shifts converted to proper SSE2 vector shifts when the shift
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; amounts are the same.
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; Note that x86 does have ashr
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define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
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; X32-LABEL: shift1a:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
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; X32-NEXT: psrad $31, %xmm0
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; X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
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; X32-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
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; X32-NEXT: movdqa %xmm1, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift1a:
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; X64: # BB#0: # %entry
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; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
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; X64-NEXT: psrad $31, %xmm0
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; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
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; X64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
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; X64-NEXT: movdqa %xmm1, (%rdi)
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; X64-NEXT: retq
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entry:
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%ashr = ashr <2 x i64> %val, < i64 32, i64 32 >
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store <2 x i64> %ashr, <2 x i64>* %dst
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ret void
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}
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define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
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; X32-LABEL: shift2a:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: psrad $5, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift2a:
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; X64: # BB#0: # %entry
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; X64-NEXT: psrad $5, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%ashr = ashr <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
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store <4 x i32> %ashr, <4 x i32>* %dst
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ret void
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}
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define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
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; X32-LABEL: shift2b:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32-NEXT: psrad %xmm1, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift2b:
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; X64: # BB#0: # %entry
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; X64-NEXT: movd %esi, %xmm1
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; X64-NEXT: psrad %xmm1, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%1 = insertelement <4 x i32> %0, i32 %amt, i32 1
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%2 = insertelement <4 x i32> %1, i32 %amt, i32 2
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%3 = insertelement <4 x i32> %2, i32 %amt, i32 3
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%ashr = ashr <4 x i32> %val, %3
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store <4 x i32> %ashr, <4 x i32>* %dst
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ret void
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}
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define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
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; X32-LABEL: shift3a:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: psraw $5, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift3a:
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; X64: # BB#0: # %entry
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; X64-NEXT: psraw $5, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%ashr = ashr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
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store <8 x i16> %ashr, <8 x i16>* %dst
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ret void
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}
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define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
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; X32-LABEL: shift3b:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movd %ecx, %xmm1
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; X32-NEXT: psraw %xmm1, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift3b:
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; X64: # BB#0: # %entry
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; X64-NEXT: movzwl %si, %eax
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; X64-NEXT: movd %eax, %xmm1
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; X64-NEXT: psraw %xmm1, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
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%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
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%2 = insertelement <8 x i16> %1, i16 %amt, i32 2
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%3 = insertelement <8 x i16> %2, i16 %amt, i32 3
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%4 = insertelement <8 x i16> %3, i16 %amt, i32 4
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%5 = insertelement <8 x i16> %4, i16 %amt, i32 5
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%6 = insertelement <8 x i16> %5, i16 %amt, i32 6
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%7 = insertelement <8 x i16> %6, i16 %amt, i32 7
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%ashr = ashr <8 x i16> %val, %7
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store <8 x i16> %ashr, <8 x i16>* %dst
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ret void
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}
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