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192 lines
6.5 KiB
LLVM
192 lines
6.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64
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; test vector shifts converted to proper SSE2 vector shifts when the shift
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; amounts are the same when using a shuffle splat.
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define void @shift1a(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
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; X32-LABEL: shift1a:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movq {{.*#+}} xmm1 = xmm1[0],zero
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; X32-NEXT: psllq %xmm1, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift1a:
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; X64: # BB#0: # %entry
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; X64-NEXT: psllq %xmm1, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
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%shl = shl <2 x i64> %val, %shamt
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store <2 x i64> %shl, <2 x i64>* %dst
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ret void
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}
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; shift1b can't use a packed shift but can shift lanes separately and shuffle back together
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define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
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; X32-LABEL: shift1b:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
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; X32-NEXT: movdqa %xmm0, %xmm3
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; X32-NEXT: psllq %xmm2, %xmm3
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; X32-NEXT: movq {{.*#+}} xmm1 = xmm1[0],zero
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; X32-NEXT: psllq %xmm1, %xmm0
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; X32-NEXT: movsd {{.*#+}} xmm3 = xmm0[0],xmm3[1]
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; X32-NEXT: movapd %xmm3, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift1b:
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; X64: # BB#0: # %entry
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; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
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; X64-NEXT: movdqa %xmm0, %xmm3
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; X64-NEXT: psllq %xmm2, %xmm3
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; X64-NEXT: psllq %xmm1, %xmm0
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; X64-NEXT: movsd {{.*#+}} xmm3 = xmm0[0],xmm3[1]
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; X64-NEXT: movapd %xmm3, (%rdi)
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; X64-NEXT: retq
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entry:
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%shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1>
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%shl = shl <2 x i64> %val, %shamt
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store <2 x i64> %shl, <2 x i64>* %dst
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ret void
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}
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define void @shift2a(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
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; X32-LABEL: shift2a:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
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; X32-NEXT: xorps %xmm2, %xmm2
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; X32-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
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; X32-NEXT: pslld %xmm2, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift2a:
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; X64: # BB#0: # %entry
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; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
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; X64-NEXT: xorps %xmm2, %xmm2
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; X64-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
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; X64-NEXT: pslld %xmm2, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%shl = shl <4 x i32> %val, %shamt
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store <4 x i32> %shl, <4 x i32>* %dst
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ret void
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}
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define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
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; X32-LABEL: shift2b:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
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; X32-NEXT: xorps %xmm2, %xmm2
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; X32-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
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; X32-NEXT: pslld %xmm2, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift2b:
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; X64: # BB#0: # %entry
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; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
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; X64-NEXT: xorps %xmm2, %xmm2
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; X64-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
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; X64-NEXT: pslld %xmm2, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1>
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%shl = shl <4 x i32> %val, %shamt
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store <4 x i32> %shl, <4 x i32>* %dst
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ret void
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}
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define void @shift2c(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
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; X32-LABEL: shift2c:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
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; X32-NEXT: xorps %xmm2, %xmm2
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; X32-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
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; X32-NEXT: pslld %xmm2, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift2c:
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; X64: # BB#0: # %entry
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; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
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; X64-NEXT: xorps %xmm2, %xmm2
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; X64-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
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; X64-NEXT: pslld %xmm2, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%shl = shl <4 x i32> %val, %shamt
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store <4 x i32> %shl, <4 x i32>* %dst
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ret void
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}
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define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
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; X32-LABEL: shift3a:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pextrw $6, %xmm1, %ecx
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; X32-NEXT: movd %ecx, %xmm1
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; X32-NEXT: psllw %xmm1, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift3a:
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; X64: # BB#0: # %entry
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; X64-NEXT: pextrw $6, %xmm1, %eax
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; X64-NEXT: movd %eax, %xmm1
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; X64-NEXT: psllw %xmm1, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
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%shl = shl <8 x i16> %val, %shamt
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store <8 x i16> %shl, <8 x i16>* %dst
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ret void
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}
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define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
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; X32-LABEL: shift3b:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movd %ecx, %xmm1
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; X32-NEXT: psllw %xmm1, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift3b:
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; X64: # BB#0: # %entry
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; X64-NEXT: movzwl %si, %eax
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; X64-NEXT: movd %eax, %xmm1
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; X64-NEXT: psllw %xmm1, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
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%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
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%2 = insertelement <8 x i16> %1, i16 %amt, i32 2
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%3 = insertelement <8 x i16> %2, i16 %amt, i32 3
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%4 = insertelement <8 x i16> %3, i16 %amt, i32 4
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%5 = insertelement <8 x i16> %4, i16 %amt, i32 5
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%6 = insertelement <8 x i16> %5, i16 %amt, i32 6
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%7 = insertelement <8 x i16> %6, i16 %amt, i32 7
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%shl = shl <8 x i16> %val, %7
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store <8 x i16> %shl, <8 x i16>* %dst
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ret void
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}
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