mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-22 10:42:39 +01:00
3bbfdfb241
The Legalizer expands the operations of urem/srem into a div+mul+sub or divrem when those are legal/custom. This patch changes the cost-model to reflect that cost. Since there is no 'divrem' Instruction in LLVM IR, the cost of divrem is assumed to be the same as div+mul+sub since the three operations will need to be executed at runtime regardless. Patch co-authored by David Sherwood (@david-arm) Reviewed By: RKSimon, paulwalker-arm Differential Revision: https://reviews.llvm.org/D103799 |
||
---|---|---|
.. | ||
add-cast-vect.ll | ||
arith-overflow.ll | ||
arith-ssat.ll | ||
arith-usat.ll | ||
arith.ll | ||
cast_ldst.ll | ||
cast.ll | ||
cmps.ll | ||
control-flow.ll | ||
divrem.ll | ||
fparith.ll | ||
freeshift.ll | ||
gep.ll | ||
immediates.ll | ||
insertelement.ll | ||
intrinsic-cost-kinds.ll | ||
lit.local.cfg | ||
load_store.ll | ||
logicalop.ll | ||
memcpy.ll | ||
mul-cast-vect.ll | ||
mve-abs.ll | ||
mve-active_lane_mask.ll | ||
mve-cmp.ll | ||
mve-gather-scatter-cost.ll | ||
mve-minmax.ll | ||
mve-vecreduce-add.ll | ||
reduce-add.ll | ||
reduce-and.ll | ||
reduce-or.ll | ||
reduce-smax.ll | ||
reduce-smin.ll | ||
reduce-umax.ll | ||
reduce-umin.ll | ||
select.ll | ||
shl-cast-vect.ll | ||
shuffle.ll | ||
sub-cast-vect.ll | ||
target-intrinsics.ll |