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a16c309109
Arm v8.1-M supports the VMOV instructions that move a half-precision value to and from a GPR, but not if the GPR is SP or PC. To fix this, I've changed those instructions to use the rGPR register class instead of GPR. rGPR always excludes PC, and it excludes SP except in the presence of the HasV8Ops target feature (i.e. Arm v8-A). So the effect is that VMOV.F16 to and from PC is now illegal everywhere, but VMOV.F16 to and from SP is illegal only on non-v8-A cores (which I believe is all as it should be). Reviewers: dmgreen, samparker, SjoerdMeijer, ostannard Reviewed By: ostannard Subscribers: ostannard, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60704 llvm-svn: 362942
25 lines
754 B
ArmAsm
25 lines
754 B
ArmAsm
// RUN: not llvm-mc -triple=thumbv8.2a-none-eabi -mattr=+fp-armv8,+fullfp16 -show-encoding < %s 2>%t \
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// RUN: | FileCheck %s
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// RUN: FileCheck --check-prefix=ERROR < %t %s
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# CHECK: vmov.f16 r0, s13 @ encoding: [0x16,0xee,0x90,0x09]
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vmov.f16 r0, s13
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# CHECK: vmov.f16 s21, r1 @ encoding: [0x0a,0xee,0x90,0x19]
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vmov.f16 s21, r1
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# CHECK: vmov.f16 s2, sp @ encoding: [0x01,0xee,0x10,0xd9]
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vmov.f16 s2, sp
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# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
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# ERROR: operand must be a register in range [r0, r14]
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vmov.f16 s3, pc
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# CHECK: vmov.f16 sp, s5 @ encoding: [0x12,0xee,0x90,0xd9]
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vmov.f16 sp, s5
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# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
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# ERROR: operand must be a register in range [r0, r14]
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vmov.f16 pc, s8
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