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ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
95 lines
3.0 KiB
C++
95 lines
3.0 KiB
C++
//==-- AArch64TargetMachine.h - Define TargetMachine for AArch64 -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the AArch64 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef AArch64TARGETMACHINE_H
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#define AArch64TARGETMACHINE_H
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#include "AArch64InstrInfo.h"
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#include "AArch64ISelLowering.h"
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#include "AArch64Subtarget.h"
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#include "AArch64FrameLowering.h"
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#include "AArch64SelectionDAGInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/MC/MCStreamer.h"
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namespace llvm {
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class AArch64TargetMachine : public LLVMTargetMachine {
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protected:
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AArch64Subtarget Subtarget;
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private:
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const DataLayout DL;
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AArch64InstrInfo InstrInfo;
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AArch64TargetLowering TLInfo;
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AArch64FrameLowering FrameLowering;
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AArch64SelectionDAGInfo TSInfo;
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public:
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AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool IsLittleEndian);
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const AArch64Subtarget *getSubtargetImpl() const override {
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return &Subtarget;
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}
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const AArch64TargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const DataLayout *getDataLayout() const override { return &DL; }
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const AArch64FrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const AArch64RegisterInfo *getRegisterInfo() const override {
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return &InstrInfo.getRegisterInfo();
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}
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const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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// Pass Pipeline Configuration
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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/// \brief Register AArch64 analysis passes with a pass manager.
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void addAnalysisPasses(PassManagerBase &PM) override;
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};
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// AArch64leTargetMachine - AArch64 little endian target machine.
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//
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class AArch64leTargetMachine : public AArch64TargetMachine {
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virtual void anchor();
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public:
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AArch64leTargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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// AArch64beTargetMachine - AArch64 big endian target machine.
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//
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class AArch64beTargetMachine : public AArch64TargetMachine {
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virtual void anchor();
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public:
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AArch64beTargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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} // end namespace llvm
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#endif
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