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eb66b33867
I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
66 lines
1.9 KiB
C++
66 lines
1.9 KiB
C++
//===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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namespace llvm {
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class SIRegisterInfo;
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class TargetRegisterInfo;
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namespace AMDGPU {
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enum {
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SGPRRegBankID = 0,
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VGPRRegBankID = 1,
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NumRegisterBanks
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};
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} // End AMDGPU namespace.
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/// This class provides the information for the target register banks.
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class AMDGPUGenRegisterBankInfo : public RegisterBankInfo {
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protected:
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#define GET_TARGET_REGBANK_CLASS
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#include "AMDGPUGenRegisterBank.inc"
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};
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class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
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const SIRegisterInfo *TRI;
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/// See RegisterBankInfo::applyMapping.
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void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
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const RegisterBankInfo::InstructionMapping &
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getInstrMappingForLoad(const MachineInstr &MI) const;
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public:
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AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI);
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unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
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unsigned Size) const override;
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const RegisterBank &
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getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
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InstructionMappings
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getInstrAlternativeMappings(const MachineInstr &MI) const override;
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const InstructionMapping &
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getInstrMapping(const MachineInstr &MI) const override;
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};
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} // End llvm namespace.
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#endif
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