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4e7a3e05a1
For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
41 lines
1.4 KiB
TableGen
41 lines
1.4 KiB
TableGen
//===-- HexagonIntrinsicsDerived.td - Derived intrinsics ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Multiply 64-bit and use lower result
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//
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// Optimized with intrinisics accumulates
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//
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def : Pat <(mul DoubleRegs:$src1, DoubleRegs:$src2),
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(i64
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(A2_combinew
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(M2_maci
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(M2_maci
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(i32
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(EXTRACT_SUBREG
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(i64
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(M2_dpmpyuu_s0 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
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isub_lo)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
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isub_lo)))),
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isub_hi)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), isub_lo)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), isub_hi))),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), isub_lo)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), isub_hi))),
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(i32
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(EXTRACT_SUBREG
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(i64
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(M2_dpmpyuu_s0
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), isub_lo)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
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isub_lo)))), isub_lo))))>;
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