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b47927165c
In testing, we've found yet another miscompile caused by the new tables. And this one is even less clear how to fix (we could teach it to fold a 16-bit load instead of the 32-bit load it wants, or block folding entirely). Also, the approach to excluding instructions seems increasingly to not scale well. I have left a more detailed analysis on the review log for the original patch (https://reviews.llvm.org/D32684) along with suggested path forward. I will land an additional test case that I wrote which covers the code that was miscompiling (folding into the output of `pextrw`) in a subsequent commit to keep this a pure revert. For each commit reverted here, I've restricted the revert to the non-test code touching the x86 fold table emission until the last commit where I did revert the test updates. This means the *new* test cases added for `insertps` and `xchg` remain untouched (and continue to pass). Reverted commits: r304540: [X86] Don't fold into memory operands into insertps in the ... r304347: [TableGen] Adapt more places to getValueAsString now ... r304163: [X86] Don't fold away the memory operand of an xchg. r304123: Don't capture a temporary std::string in a StringRef. r304122: Resubmit "[X86] Adding new LLVM TableGen backend that ..." Original commit was in r304088, and after a string of fixes was reverted previously in r304121 to fix build bots, and then re-landed in r304122. llvm-svn: 304762
80 lines
2.1 KiB
CMake
80 lines
2.1 KiB
CMake
set(LLVM_TARGET_DEFINITIONS X86.td)
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tablegen(LLVM X86GenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM X86GenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM X86GenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM X86GenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
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tablegen(LLVM X86GenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM X86GenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM X86GenFastISel.inc -gen-fast-isel)
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tablegen(LLVM X86GenCallingConv.inc -gen-callingconv)
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tablegen(LLVM X86GenSubtargetInfo.inc -gen-subtarget)
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tablegen(LLVM X86GenEVEX2VEXTables.inc -gen-x86-EVEX2VEX-tables)
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if(LLVM_BUILD_GLOBAL_ISEL)
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tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank)
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tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel)
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endif()
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add_public_tablegen_target(X86CommonTableGen)
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# Add GlobalISel files if the build option was enabled.
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set(GLOBAL_ISEL_FILES
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X86CallLowering.cpp
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X86LegalizerInfo.cpp
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X86RegisterBankInfo.cpp
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X86InstructionSelector.cpp
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)
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if(LLVM_BUILD_GLOBAL_ISEL)
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set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
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else()
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set(GLOBAL_ISEL_BUILD_FILES "")
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set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
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endif()
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set(sources
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X86AsmPrinter.cpp
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X86CallFrameOptimization.cpp
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X86ExpandPseudo.cpp
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X86FastISel.cpp
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X86FixupBWInsts.cpp
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X86FixupLEAs.cpp
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X86FixupSetCC.cpp
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X86FloatingPoint.cpp
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X86FrameLowering.cpp
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X86ISelDAGToDAG.cpp
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X86ISelLowering.cpp
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X86InterleavedAccess.cpp
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X86InstrFMA3Info.cpp
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X86InstrInfo.cpp
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X86EvexToVex.cpp
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X86MCInstLower.cpp
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X86MachineFunctionInfo.cpp
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X86MacroFusion.cpp
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X86OptimizeLEAs.cpp
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X86PadShortFunction.cpp
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X86RegisterInfo.cpp
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X86SelectionDAGInfo.cpp
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X86ShuffleDecodeConstantPool.cpp
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X86Subtarget.cpp
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X86TargetMachine.cpp
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X86TargetObjectFile.cpp
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X86TargetTransformInfo.cpp
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X86VZeroUpper.cpp
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X86WinAllocaExpander.cpp
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X86WinEHState.cpp
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X86CallingConv.cpp
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${GLOBAL_ISEL_BUILD_FILES}
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)
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add_llvm_target(X86CodeGen ${sources})
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add_subdirectory(AsmParser)
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add_subdirectory(Disassembler)
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add_subdirectory(InstPrinter)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(TargetInfo)
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add_subdirectory(Utils)
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