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74 lines
2.4 KiB
TableGen
74 lines
2.4 KiB
TableGen
//===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the SystemZ instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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include "SystemZInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// SystemZ Specific Node Definitions.
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//===----------------------------------------------------------------------===//
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def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInFlag]>;
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let neverHasSideEffects = 1 in
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def NOP : Pseudo<(outs), (ins), "# no-op", []>;
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions...
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//
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// FIXME: Provide proper encoding!
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let isReturn = 1, isTerminator = 1 in {
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def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
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}
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//===----------------------------------------------------------------------===//
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// Move Instructions
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// FIXME: Provide proper encoding!
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let neverHasSideEffects = 1 in {
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def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
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"lgr\t{$dst, $src}",
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[]>;
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}
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// FIXME: Provide proper encoding!
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOV64ri : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
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"lghi\t{$dst, $src}",
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[(set GR64:$dst, imm:$src)]>;
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}
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions
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let isTwoAddress = 1 in {
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let Defs = [PSW] in {
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let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
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// FIXME: Provide proper encoding!
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def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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"agr\t{$dst, $src2}",
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[(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
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(implicit PSW)]>;
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}
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// FIXME: Provide proper encoding!
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def ADD64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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"aghi\t{$dst, $src2}",
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[(set GR64:$dst, (add GR64:$src1, imm:$src2)),
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(implicit PSW)]>;
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} // Defs = [PSW]
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} // isTwoAddress = 1
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