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cf31bae691
For the following function:
double fn1(double d0, double d1, double d2) {
double a = -d0 - d1 * d2;
return a;
}
on ARM, LLVM generates code along the lines of
vneg.f64 d0, d0
vmls.f64 d0, d1, d2
i.e., a negate and a multiply-subtract.
The attached patch adds instruction selection patterns to allow it to generate the single instruction
vnmla.f64 d0, d1, d2
(multiply-add with negation) instead, like GCC does.
Committed on behalf of @gergo- (Gergö Barany)
Differential Revision: https://reviews.llvm.org/D35911
llvm-svn: 313972
167 lines
3.2 KiB
LLVM
167 lines
3.2 KiB
LLVM
; RUN: llc -mtriple=arm-eabihf -mattr=+vfp2 %s -o - \
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; RUN: | FileCheck %s -check-prefix=VFP2
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; RUN: llc -mtriple=arm-eabihf -mattr=+vfp3 %s -o - \
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; RUN: | FileCheck %s -check-prefix=VFP3
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; RUN: llc -mtriple=arm-eabihf -mattr=+neon %s -o - \
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; RUN: | FileCheck %s -check-prefix=NEON
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; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \
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; RUN: | FileCheck %s -check-prefix=A8
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; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -regalloc=basic %s -o - \
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; RUN: | FileCheck %s -check-prefix=A8
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; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \
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; RUN: | FileCheck %s -check-prefix=A8U
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; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \
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; RUN: | FileCheck %s -check-prefix=A8U
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define float @t1(float %acc, float %a, float %b) nounwind {
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entry:
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; VFP2-LABEL: t1:
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; VFP2: vnmla.f32
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; VFP3-LABEL: t1:
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; VFP3: vnmla.f32
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; NEON-LABEL: t1:
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; NEON: vnmla.f32
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; A8U-LABEL: t1:
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; A8U: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
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; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
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; A8-LABEL: t1:
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; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
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; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
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%0 = fmul float %a, %b
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%1 = fsub float -0.0, %0
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%2 = fsub float %1, %acc
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ret float %2
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}
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define float @t2(float %acc, float %a, float %b) nounwind {
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entry:
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; VFP2-LABEL: t2:
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; VFP2: vnmla.f32
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; VFP3-LABEL: t2:
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; VFP3: vnmla.f32
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; NEON-LABEL: t2:
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; NEON: vnmla.f32
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; A8U-LABEL: t2:
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; A8U: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
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; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
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; A8-LABEL: t2:
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; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
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; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
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%0 = fmul float %a, %b
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%1 = fmul float -1.0, %0
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%2 = fsub float %1, %acc
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ret float %2
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}
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define double @t3(double %acc, double %a, double %b) nounwind {
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entry:
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; VFP2-LABEL: t3:
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; VFP2: vnmla.f64
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; VFP3-LABEL: t3:
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; VFP3: vnmla.f64
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; NEON-LABEL: t3:
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; NEON: vnmla.f64
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; A8U-LABEL: t3:
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; A8U: vnmul.f64 d
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; A8U: vsub.f64 d
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; A8-LABEL: t3:
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; A8: vnmul.f64 d
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; A8: vsub.f64 d
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%0 = fmul double %a, %b
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%1 = fsub double -0.0, %0
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%2 = fsub double %1, %acc
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ret double %2
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}
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define double @t4(double %acc, double %a, double %b) nounwind {
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entry:
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; VFP2-LABEL: t4:
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; VFP2: vnmla.f64
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; VFP3-LABEL: t4:
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; VFP3: vnmla.f64
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; NEON-LABEL: t4:
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; NEON: vnmla.f64
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; A8U-LABEL: t4:
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; A8U: vnmul.f64 d
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; A8U: vsub.f64 d
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; A8-LABEL: t4:
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; A8: vnmul.f64 d
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; A8: vsub.f64 d
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%0 = fmul double %a, %b
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%1 = fmul double -1.0, %0
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%2 = fsub double %1, %acc
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ret double %2
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}
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define double @t5(double %acc, double %a, double %b) nounwind {
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entry:
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; VFP2-LABEL: t5:
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; VFP2: vnmla.f64
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; VFP3-LABEL: t5:
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; VFP3: vnmla.f64
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; NEON-LABEL: t5:
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; NEON: vnmla.f64
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; A8U-LABEL: t5:
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; A8U: vmul.f64 d
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; A8U: vsub.f64 d
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; A8-LABEL: t5:
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; A8: vmul.f64 d
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; A8: vsub.f64 d
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%0 = fsub double -0.0, %acc
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%1 = fmul double %a, %b
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%2 = fsub double %0, %1
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ret double %2
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}
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define float @t6(float %acc, float %a, float %b) nounwind {
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entry:
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; VFP2-LABEL: t6:
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; VFP2: vnmla.f32
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; VFP3-LABEL: t6:
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; VFP3: vnmla.f32
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; NEON-LABEL: t6:
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; NEON: vnmla.f32
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; A8U-LABEL: t6:
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; A8U: vmul.f32 d
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; A8U: vsub.f32 d
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; A8-LABEL: t6:
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; A8: vmul.f32 s
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; A8: vsub.f32 s
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%0 = fsub float -0.0, %acc
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%1 = fmul float %a, %b
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%2 = fsub float %0, %1
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ret float %2
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}
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