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llvm-mirror/test/CodeGen/ARM/mul_const.ll
Saleem Abdulrasool 53e8c5a4af ARM: fixup more tests to specify the target more explicitly
This changes the tests that were targeting ARM EABI to explicitly specify the
environment rather than relying on the default.  This breaks with the new
Windows on ARM support when running the tests on Windows where the default
environment is no longer EABI.

Take the opportunity to avoid a pointless redirect (helps when trying to debug
with providing a command line invocation which can be copy and pasted) and
removing a few greps in favour of FileCheck.

llvm-svn: 205541
2014-04-03 16:01:44 +00:00

86 lines
1.6 KiB
LLVM

; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
define i32 @t9(i32 %v) nounwind readnone {
entry:
; CHECK-LABEL: t9:
; CHECK: add r0, r0, r0, lsl #3
%0 = mul i32 %v, 9
ret i32 %0
}
define i32 @t7(i32 %v) nounwind readnone {
entry:
; CHECK-LABEL: t7:
; CHECK: rsb r0, r0, r0, lsl #3
%0 = mul i32 %v, 7
ret i32 %0
}
define i32 @t5(i32 %v) nounwind readnone {
entry:
; CHECK-LABEL: t5:
; CHECK: add r0, r0, r0, lsl #2
%0 = mul i32 %v, 5
ret i32 %0
}
define i32 @t3(i32 %v) nounwind readnone {
entry:
; CHECK-LABEL: t3:
; CHECK: add r0, r0, r0, lsl #1
%0 = mul i32 %v, 3
ret i32 %0
}
define i32 @t12288(i32 %v) nounwind readnone {
entry:
; CHECK-LABEL: t12288:
; CHECK: add r0, r0, r0, lsl #1
; CHECK: lsl{{.*}}#12
%0 = mul i32 %v, 12288
ret i32 %0
}
define i32 @tn9(i32 %v) nounwind readnone {
entry:
; CHECK-LABEL: tn9:
; CHECK: add r0, r0, r0, lsl #3
; CHECK: rsb r0, r0, #0
%0 = mul i32 %v, -9
ret i32 %0
}
define i32 @tn7(i32 %v) nounwind readnone {
entry:
; CHECK-LABEL: tn7:
; CHECK: sub r0, r0, r0, lsl #3
%0 = mul i32 %v, -7
ret i32 %0
}
define i32 @tn5(i32 %v) nounwind readnone {
entry:
; CHECK-LABEL: tn5:
; CHECK: add r0, r0, r0, lsl #2
; CHECK: rsb r0, r0, #0
%0 = mul i32 %v, -5
ret i32 %0
}
define i32 @tn3(i32 %v) nounwind readnone {
entry:
; CHECK-LABEL: tn3:
; CHECK: sub r0, r0, r0, lsl #2
%0 = mul i32 %v, -3
ret i32 %0
}
define i32 @tn12288(i32 %v) nounwind readnone {
entry:
; CHECK-LABEL: tn12288:
; CHECK: sub r0, r0, r0, lsl #2
; CHECK: lsl{{.*}}#12
%0 = mul i32 %v, -12288
ret i32 %0
}