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a08d5736a7
Summary:
PerformVMOVRRDCombine ommits adding a offset
of 4 to the PointerInfo, when converting a
f64 = load[M]
to
{i32, i32} = {load[M], load[M + 4]}
Which would allow the machine scheduller
to break dependencies with the second load.
- pr42638
Reviewers: eli.friedman, dmgreen, ostannard
Reviewed By: ostannard
Subscribers: ostannard, javed.absar, kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64870
llvm-svn: 366423
34 lines
1.2 KiB
LLVM
34 lines
1.2 KiB
LLVM
; RUN: llc -stop-after=machine-scheduler -debug-only dagcombine,selectiondag -o - %s 2>&1 | FileCheck %s
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; REQUIRES: asserts
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; pr42638
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target triple = "armv8r-arm-none-eabi"
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%struct.__va_list = type { i8* }
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define double @foo(i32 %P0, ...) #0 {
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entry:
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%V1 = alloca [8 x i8], align 8
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%vl = alloca %struct.__va_list, align 4
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%0 = getelementptr inbounds [8 x i8], [8 x i8]* %V1, i32 0, i32 0
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call void asm sideeffect "", "r"(i8* nonnull %0)
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%1 = bitcast %struct.__va_list* %vl to i8*
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call void @llvm.va_start(i8* nonnull %1)
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%2 = bitcast %struct.__va_list* %vl to double**
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%argp.cur3 = load double*, double** %2, align 4
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%v.sroa.0.0.copyload = load double, double* %argp.cur3, align 4
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ret double %v.sroa.0.0.copyload
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}
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declare void @llvm.va_start(i8*)
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attributes #0 = { "target-cpu"="cortex-r52" "target-features"="-fp64" }
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; Ensures that the machine scheduler does not move accessing the upper
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; 32 bits of the double to before actually storing it to memory
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; CHECK: Creating new node: {{.*}} = add FrameIndex:i32<2>, Constant:i32<4>
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; CHECK-NEXT: Creating new node: {{.*}} i32,ch = load<(load 4 from [[MEM:%.*]] + 4)>
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; CHECK: INLINEASM
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; CHECK: (load 4 from [[MEM]] + 4)
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; CHECK-NOT: (store 4 into [[MEM]] + 4)
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