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llvm-mirror/test/CodeGen/RISCV
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Guozhi Wei bba33a7e31 [MBP] Disable aggressive loop rotate in plain mode 
Patch https://reviews.llvm.org/D43256 introduced more aggressive loop layout optimization which depends on profile information. If profile information is not available, the statically estimated profile information(generated by BranchProbabilityInfo.cpp) is used. If user program doesn't behave as BranchProbabilityInfo.cpp expected, the layout may be worse.

To be conservative this patch restores the original layout algorithm in plain mode. But user can still try the aggressive layout optimization with -force-precise-rotation-cost=true.

Differential Revision: https://reviews.llvm.org/D65673

llvm-svn: 368339
2019-08-08 20:25:23 +00:00
..
add-before-shl.ll [RISCV] Fix ICE in isDesirableToCommuteWithShift 2019-07-09 16:24:16 +00:00
addc-adde-sube-subc.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
addcarry.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
align.ll
alloca.ll
alu8.ll
alu16.ll
alu32.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
alu64.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
analyze-branch.ll
arith-with-overflow.ll
atomic-cmpxchg-flag.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
atomic-cmpxchg.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
atomic-fence.ll
atomic-load-store.ll
atomic-rmw.ll [MBP] Disable aggressive loop rotate in plain mode 2019-08-08 20:25:23 +00:00
bare-select.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
blockaddress.ll
branch-relaxation.ll [RISCV] Match GNU tools canonical JALR and add aliases 2019-07-16 04:56:43 +00:00
branch.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
bswap-ctlz-cttz-ctpop.ll
byval.ll
callee-saved-fpr32s.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
callee-saved-fpr64s.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
callee-saved-gprs.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
calling-conv-ilp32-ilp32f-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-ilp32.ll
calling-conv-ilp32d.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-ilp32f-ilp32d-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-lp64-lp64f-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-lp64-lp64f-lp64d-common.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
calling-conv-lp64.ll
calling-conv-rv32f-ilp32.ll
calling-conv-sext-zext.ll
calls.ll [RISCV] Lower calls through PLT 2019-06-18 14:29:45 +00:00
codemodel-lowering.ll [RISCV] Implement adding a displacement to a BlockAddress 2019-04-05 08:40:57 +00:00
compress-inline-asm.ll
compress.ll
disable-tail-calls.ll
div.ll
double-arith.ll
double-bitmanip-dagcombines.ll
double-br-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
double-calling-conv.ll
double-convert.ll
double-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
double-frem.ll
double-imm.ll
double-intrinsics.ll
double-mem.ll
double-previous-failure.ll
double-select-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
double-stack-spill-restore.ll
dwarf-eh.ll [RISCV][NFC] Remove outdated TODO from test/CodeGen/RISCV/dwarf-eh.ll 2019-07-17 14:04:48 +00:00
exception-pointer-register.ll [RISCV] Specify registers used in DWARF exception handling 2019-07-08 09:16:47 +00:00
fixups-diff.ll
fixups-relax-diff.ll [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame. 2019-07-19 02:03:34 +00:00
float-arith.ll
float-bit-preserving-dagcombines.ll [RISCV] Support Bit-Preserving FP in F/D Extensions 2019-06-07 12:20:14 +00:00
float-bitmanip-dagcombines.ll
float-br-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
float-convert.ll
float-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
float-frem.ll
float-imm.ll
float-intrinsics.ll
float-mem.ll
float-select-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
flt-rounds.ll
fp128.ll
frame-info.ll [RISCV] Add CFI directives for RISCV prologue/epilog. 2019-06-12 03:04:22 +00:00
frame.ll
frameaddr-returnaddr.ll
get-setcc-result-type.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
hoist-global-addr-base.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
i32-icmp.ll
imm-cse.ll [RISCV] Add RISCV-specific TargetTransformInfo 2019-06-21 13:36:09 +00:00
imm.ll
indirectbr.ll [RISCV] Match GNU tools canonical JALR and add aliases 2019-07-16 04:56:43 +00:00
init-array.ll [IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format 2019-05-15 02:35:32 +00:00
inline-asm-abi-names.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-clobbers.ll [RISCV] Add support for lowering floating point inlineasm clobbers 2019-07-31 09:07:21 +00:00
inline-asm-d-abi-names.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-d-constraint-f.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-f-abi-names.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-f-constraint-f.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-i-constraint-i1.ll [TargetLowering] Extend bool args to inline-asm according to getBooleanType 2019-05-22 16:16:15 +00:00
inline-asm-invalid.ll Emit diagnostic if an inline asm constraint requires an immediate 2019-08-03 05:52:47 +00:00
inline-asm.ll [RISCV] Support z and i operand modifiers 2019-07-08 05:00:26 +00:00
interrupt-attr-args-error.ll
interrupt-attr-invalid.ll
interrupt-attr-nocall.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
interrupt-attr-ret-error.ll
interrupt-attr.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
jumptable.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
large-stack.ll
legalize-fneg.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
lit.local.cfg
lsr-legaladdimm.ll
mattr-invalid-combination.ll
mem64.ll
mem.ll
mul.ll
musttail-call.ll
option-norelax.ll
option-norvc.ll
option-relax.ll
option-rvc.ll [RISCV] Match GNU tools canonical JALR and add aliases 2019-07-16 04:56:43 +00:00
pic-models.ll [RISCV] Add lowering of addressing sequences for PIC 2019-06-11 12:57:47 +00:00
pr40333.ll
prefetch.ll
readcyclecounter.ll [RISCV] Support @llvm.readcyclecounter() Intrinsic 2019-07-05 12:35:21 +00:00
rem.ll
remat.ll [MBP] Disable aggressive loop rotate in plain mode 2019-08-08 20:25:23 +00:00
rotl-rotr.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
rv32e.ll
rv32i-rv64i-float-double.ll
rv64d-double-convert.ll
rv64f-float-convert.ll
rv64i-exhaustive-w-insts.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
rv64i-tricky-shifts.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
rv64i-w-insts-legalization.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
rv64m-exhaustive-w-insts.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
rv64m-w-insts-legalization.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
sdata-limit-0.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
sdata-limit-4.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
sdata-limit-8.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
sdata-local-sym.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
select-cc.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
select-optimize-multiple.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
select-optimize-multiple.mir [RISCV] Fix test after r363757 2019-06-19 03:18:48 +00:00
setcc-logic.ll
sext-zext-trunc.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
shift-masked-shamt.ll
shifts.ll [RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS 2019-04-16 14:38:32 +00:00
split-offsets.ll [DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting 2019-06-17 10:54:12 +00:00
stack-realignment-unsupported.ll [RISCV] Minimal stack realignment support 2019-08-08 14:40:54 +00:00
stack-realignment.ll [RISCV] Minimal stack realignment support 2019-08-08 14:40:54 +00:00
tail-calls.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
target-abi-invalid.ll
target-abi-valid.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
tls-models.ll [RISCV] Add lowering of global TLS addresses 2019-06-19 08:40:59 +00:00
umulo-128-legalisation-lowering.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
vararg.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
wide-mem.ll
zext-with-load-is-free.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00