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b1dba2466d
Mark the FREM SelectionDAG node as Expand, which is necessary in order to support the frem IR instruction on RISC-V. This is expanded into a library call. Adds the corresponding test. Previously, this would have triggered an assertion at instruction selection time. Differential Revision: https://reviews.llvm.org/D54159 Patch by Luís Marques. llvm-svn: 346958
17 lines
526 B
LLVM
17 lines
526 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32ID %s
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define double @frem_f64(double %a, double %b) nounwind {
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; RV32ID-LABEL: frem_f64:
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; RV32ID: # %bb.0:
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; RV32ID-NEXT: addi sp, sp, -16
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; RV32ID-NEXT: sw ra, 12(sp)
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; RV32ID-NEXT: call fmod
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; RV32ID-NEXT: lw ra, 12(sp)
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; RV32ID-NEXT: addi sp, sp, 16
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; RV32ID-NEXT: ret
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%1 = frem double %a, %b
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ret double %1
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}
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