Matt Arsenault 93828aab9b AMDGPU: Expand register indexing pseudos in custom inserter ... This is to help moveSILowerControlFlow to before regalloc. There are a couple of tradeoffs with this. The complete CFG is visible to more passes, the loop body avoids an extra copy of m0, vcc isn't required, and immediate offsets can be shrunk into s_movk_i32. The disadvantage is the register allocator doesn't understand that the single lane's vector is dead within the loop body, so an extra register is used to outlive the loop block when expanding the VGPR -> m0 loop. This also now results in worse waitcnt insertion before the loop instead of after for pending operations at the point of the indexing, but that should be fixed by future improvements to cross block waitcnt insertion. v_movreld_b32's operands are now modeled more correctly since vdst is not a true output. This is kind of a hack to treat vdst as a use operand. Extra checking is required in the verifier since I can't seem to get tablegen to emit an implicit operand for a virtual register. llvm-svn: 275934		2016-07-19 00:35:03 +00:00
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AMDGPUDisassembler.cpp	AMDGPU: Expand register indexing pseudos in custom inserter	2016-07-19 00:35:03 +00:00
AMDGPUDisassembler.h	[AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers.	2016-05-24 12:05:16 +00:00
CMakeLists.txt	[AMDGPU][llvm-mc] s_getreg/setreg* - hwreg - factor out strings/literals etc.	2016-05-26 17:00:33 +00:00
LLVMBuild.txt