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71790c948e
Summary: v2: don't count SGPRs spilled to scratch twice I think this is sufficient. It doesn't count private memory usage, which happens often and uses scratch but isn't technically a spill. The private memory usage can be computed by: [scratch_per_thread - vgpr_spills - a random multiple of SGPR spills]. The fact SGPR spills add very high numbers to the scratch size make that computation a guessing game, but I don't have a solution to that. Reviewers: tstellarAMD Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D22197 llvm-svn: 275288
315 lines
12 KiB
C++
315 lines
12 KiB
C++
//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCInstrDesc.h"
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
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#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
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namespace SIInstrFlags {
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// This needs to be kept in sync with the field bits in InstSI.
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enum {
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SALU = 1 << 3,
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VALU = 1 << 4,
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SOP1 = 1 << 5,
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SOP2 = 1 << 6,
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SOPC = 1 << 7,
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SOPK = 1 << 8,
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SOPP = 1 << 9,
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VOP1 = 1 << 10,
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VOP2 = 1 << 11,
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VOP3 = 1 << 12,
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VOPC = 1 << 13,
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SDWA = 1 << 14,
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DPP = 1 << 15,
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MUBUF = 1 << 16,
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MTBUF = 1 << 17,
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SMRD = 1 << 18,
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DS = 1 << 19,
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MIMG = 1 << 20,
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FLAT = 1 << 21,
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WQM = 1 << 22,
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VGPRSpill = 1 << 23,
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VOPAsmPrefer32Bit = 1 << 24,
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Gather4 = 1 << 25
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};
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}
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namespace llvm {
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namespace AMDGPU {
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enum OperandType {
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/// Operand with register or 32-bit immediate
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OPERAND_REG_IMM32 = MCOI::OPERAND_FIRST_TARGET,
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/// Operand with register or inline constant
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OPERAND_REG_INLINE_C,
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/// Operand with 32-bit immediate that uses the constant bus. The standard
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/// OPERAND_IMMEDIATE should be used for special immediates such as source
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/// modifiers.
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OPERAND_KIMM32
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};
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}
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}
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namespace SIInstrFlags {
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enum Flags {
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// First 4 bits are the instruction encoding
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VM_CNT = 1 << 0,
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EXP_CNT = 1 << 1,
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LGKM_CNT = 1 << 2
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};
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// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
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// The result is true if any of these tests are true.
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enum ClassFlags {
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S_NAN = 1 << 0, // Signaling NaN
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Q_NAN = 1 << 1, // Quiet NaN
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N_INFINITY = 1 << 2, // Negative infinity
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N_NORMAL = 1 << 3, // Negative normal
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N_SUBNORMAL = 1 << 4, // Negative subnormal
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N_ZERO = 1 << 5, // Negative zero
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P_ZERO = 1 << 6, // Positive zero
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P_SUBNORMAL = 1 << 7, // Positive subnormal
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P_NORMAL = 1 << 8, // Positive normal
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P_INFINITY = 1 << 9 // Positive infinity
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};
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}
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// Input operand modifiers bit-masks
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// NEG and SEXT share same bit-mask because they can't be set simultaneously.
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namespace SISrcMods {
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enum {
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NEG = 1 << 0, // Floating-point negate modifier
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ABS = 1 << 1, // Floating-point absolute modifier
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SEXT = 1 << 0 // Integer sign-extend modifier
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};
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}
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namespace SIOutMods {
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enum {
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NONE = 0,
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MUL2 = 1,
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MUL4 = 2,
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DIV2 = 3
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};
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}
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namespace llvm {
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namespace AMDGPU {
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namespace EncValues { // Encoding values of enum9/8/7 operands
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enum {
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SGPR_MIN = 0,
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SGPR_MAX = 101,
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TTMP_MIN = 112,
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TTMP_MAX = 123,
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INLINE_INTEGER_C_MIN = 128,
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INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
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INLINE_INTEGER_C_MAX = 208,
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INLINE_FLOATING_C_MIN = 240,
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INLINE_FLOATING_C_MAX = 248,
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LITERAL_CONST = 255,
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VGPR_MIN = 256,
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VGPR_MAX = 511
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};
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} // namespace EncValues
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} // namespace AMDGPU
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} // namespace llvm
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namespace llvm {
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namespace AMDGPU {
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namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
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enum Id { // Message ID, width(4) [3:0].
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ID_UNKNOWN_ = -1,
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ID_INTERRUPT = 1,
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ID_GS,
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ID_GS_DONE,
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ID_SYSMSG = 15,
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ID_GAPS_LAST_, // Indicate that sequence has gaps.
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ID_GAPS_FIRST_ = ID_INTERRUPT,
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ID_SHIFT_ = 0,
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ID_WIDTH_ = 4,
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ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
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};
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enum Op { // Both GS and SYS operation IDs.
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OP_UNKNOWN_ = -1,
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OP_SHIFT_ = 4,
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// width(2) [5:4]
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OP_GS_NOP = 0,
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OP_GS_CUT,
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OP_GS_EMIT,
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OP_GS_EMIT_CUT,
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OP_GS_LAST_,
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OP_GS_FIRST_ = OP_GS_NOP,
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OP_GS_WIDTH_ = 2,
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OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_),
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// width(3) [6:4]
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OP_SYS_ECC_ERR_INTERRUPT = 1,
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OP_SYS_REG_RD,
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OP_SYS_HOST_TRAP_ACK,
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OP_SYS_TTRACE_PC,
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OP_SYS_LAST_,
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OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
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OP_SYS_WIDTH_ = 3,
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OP_SYS_MASK_ = (((1 << OP_SYS_WIDTH_) - 1) << OP_SHIFT_)
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};
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enum StreamId { // Stream ID, (2) [9:8].
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STREAM_ID_DEFAULT_ = 0,
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STREAM_ID_LAST_ = 4,
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STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
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STREAM_ID_SHIFT_ = 8,
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STREAM_ID_WIDTH_= 2,
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STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
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};
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} // namespace SendMsg
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namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
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enum Id { // HwRegCode, (6) [5:0]
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ID_UNKNOWN_ = -1,
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ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
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ID_SYMBOLIC_LAST_ = 8,
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ID_SHIFT_ = 0,
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ID_WIDTH_ = 6,
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ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
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};
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enum Offset { // Offset, (5) [10:6]
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OFFSET_DEFAULT_ = 0,
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OFFSET_SHIFT_ = 6,
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OFFSET_WIDTH_ = 5,
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OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_)
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};
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enum WidthMinusOne { // WidthMinusOne, (5) [15:11]
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WIDTH_M1_DEFAULT_ = 31,
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WIDTH_M1_SHIFT_ = 11,
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WIDTH_M1_WIDTH_ = 5,
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WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_)
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};
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} // namespace Hwreg
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} // namespace AMDGPU
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} // namespace llvm
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#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
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#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
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#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
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#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
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#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
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#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
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#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
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#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
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#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
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#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
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#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
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#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
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#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
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#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
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#define C_00B84C_USER_SGPR 0xFFFFFFC1
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#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
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#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
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#define C_00B84C_TGID_X_EN 0xFFFFFF7F
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#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
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#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
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#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
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#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
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#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
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#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
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#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
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#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
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#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
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#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
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#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
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#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
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/* CIK */
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#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
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#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
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#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
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/* */
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#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
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#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
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#define C_00B84C_LDS_SIZE 0xFF007FFF
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#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
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#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
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#define C_00B84C_EXCP_EN
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#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
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#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
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#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
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#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
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#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
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#define C_00B848_VGPRS 0xFFFFFFC0
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#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
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#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
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#define C_00B848_SGPRS 0xFFFFFC3F
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#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
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#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
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#define C_00B848_PRIORITY 0xFFFFF3FF
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#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
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#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
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#define C_00B848_FLOAT_MODE 0xFFF00FFF
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#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
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#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
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#define C_00B848_PRIV 0xFFEFFFFF
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#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
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#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
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#define C_00B848_DX10_CLAMP 0xFFDFFFFF
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#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
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#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
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#define C_00B848_DEBUG_MODE 0xFFBFFFFF
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#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
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#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
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#define C_00B848_IEEE_MODE 0xFF7FFFFF
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// Helpers for setting FLOAT_MODE
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#define FP_ROUND_ROUND_TO_NEAREST 0
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#define FP_ROUND_ROUND_TO_INF 1
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#define FP_ROUND_ROUND_TO_NEGINF 2
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#define FP_ROUND_ROUND_TO_ZERO 3
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// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
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// precision.
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#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
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#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
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#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
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#define FP_DENORM_FLUSH_OUT 1
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#define FP_DENORM_FLUSH_IN 2
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#define FP_DENORM_FLUSH_NONE 3
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// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
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// precision.
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#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
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#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
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#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
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#define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
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#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
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#define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
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#define R_SPILLED_SGPRS 0x4
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#define R_SPILLED_VGPRS 0x8
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#endif
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