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11a442d515
Invalid operation is signaled if the operand of these instructions is NaN. llvm-svn: 154545
53 lines
1.6 KiB
LLVM
53 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=32
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64
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; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2
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; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefix=NO-NAN
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define float @foo0(float %a) nounwind readnone {
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entry:
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; 32: lui $[[T0:[0-9]+]], 32767
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; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
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; 32: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 32: mtc1 $[[AND]], $f0
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; 32R2: ins $[[INS:[0-9]+]], $zero, 31, 1
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; 32R2: mtc1 $[[INS]], $f0
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; NO-NAN: abs.s
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%call = tail call float @fabsf(float %a) nounwind readnone
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ret float %call
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}
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declare float @fabsf(float) nounwind readnone
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define double @foo1(double %a) nounwind readnone {
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entry:
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; 32: lui $[[T0:[0-9]+]], 32767
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; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
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; 32: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 32: mtc1 $[[AND]], $f1
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; 32R2: ins $[[INS:[0-9]+]], $zero, 31, 1
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; 32R2: mtc1 $[[INS]], $f1
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; 64: daddiu $[[T0:[0-9]+]], $zero, 1
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; 64: dsll $[[T1:[0-9]+]], ${{[0-9]+}}, 63
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; 64: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1
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; 64: and $[[AND:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
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; 64: dmtc1 $[[AND]], $f0
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; 64R2: dins $[[INS:[0-9]+]], $zero, 63, 1
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; 64R2: dmtc1 $[[INS]], $f0
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; NO-NAN: abs.d
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%call = tail call double @fabs(double %a) nounwind readnone
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ret double %call
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}
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declare double @fabs(double) nounwind readnone
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