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The register allocator can split a live interval of a register into a set of smaller intervals. After the allocation of registers is complete, the rewriter will modify the IR to replace virtual registers with the corres- ponding physical registers. At this stage, if a register corresponding to a subregister of a virtual register is used, the rewriter will check if that subregister is undefined, and if so, it will add the <undef> flag to the machine operand. The function verifying liveness of the subregis- ter would assume that it is undefined, unless any of the subranges of the live interval proves otherwise. The problem is that the live intervals created during splitting do not have any subranges, even if the original parent interval did. This could result in the <undef> flag placed on a register that is actually defined. Differential Revision: http://reviews.llvm.org/D21189 llvm-svn: 279625
52 lines
959 B
YAML
52 lines
959 B
YAML
# RUN: llc -march=amdgcn -run-pass liveintervals -debug-only=regalloc -o /dev/null %s 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# CHECK: INTERVALS
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# CHECK: vreg0
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# CHECK-LABEL: Machine code for function test0:
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# CHECK: INTERVALS
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# CHECK: vreg0
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# CHECK-LABEL: Machine code for function test1:
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--- |
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define void @test0() { ret void }
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define void @test1() { ret void }
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...
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---
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name: test0
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registers:
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- { id: 0, class: sreg_64 }
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body: |
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bb.0:
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S_NOP 0, implicit-def %0
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S_NOP 0, implicit %0
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S_NOP 0, implicit-def undef %0.sub0
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S_NOP 0, implicit %0
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...
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---
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name: test1
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registers:
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- { id: 0, class: sreg_64 }
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
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S_BRANCH %bb.2
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bb.1:
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successors: %bb.3
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S_NOP 0, implicit-def undef %0.sub0
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S_BRANCH %bb.3
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bb.2:
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successors: %bb.3
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S_NOP 0, implicit-def %0
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S_BRANCH %bb.3
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bb.3:
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S_NOP 0
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S_NOP 0, implicit %0
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...
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